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International Conference on computer Communications and Networks (ICCCN)

作者： T. Alrabiah T.F. Znati Department of Computer Science University of Pittsburgh Pittsburgh PA USA Telecommunications Program University of Pittsburgh Pittsburgh PA USA

Development of efficient multicasting algorithms which support a wide range of quality of service requirements is crucial to the successful deployment of multimedia applications. In this paper we present a new class of low-cost, bounded delay multicast heuristics for integrated service networks. The heuristics use various techniques to find the solution to the multicast problem, if one exists. These heuristics are described and shown to be cycle free and of complexity O(zn/sup 2/) where z is the number of multicast nodes and n is the number of nodes in the network. We also show that if no delay bound was violated during the construction of the tree, the proposed heuristics give an approximation that does not exceed in average the cost of the optimal solution by more than 5%.

关键词： Routing Multicast algorithms Delay Costs Multicast protocols Intserv networks Steiner trees Internet computer science Quality of service

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Static packet routing in NoC platform using ACO-based algorithms

Static packet routing in NoC platform using ACO-based algori...

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13th International Conference on Intelligent Data Engineering and Automated Learning, IDEAL 2012

作者： Silva Jr., Luneque Nedjah, Nadia De Macedo Mourelle, Luiza Systems Engineering and Computer Science Program COPPE Federal University of Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications State University of Rio de Janeiro Brazil Department of Systems Engineering and Computation State University of Rio de Janeiro Brazil

ISBN: (纸本)9783642326387

Networks-on-Chip (NoC) have been used as an interesting option in design of communication infrastructures for embedded systems, providing a scalable structure and balancing the communication between cores. Because several data packets can be transmitted simultaneously through the network, an efficient routing strategy must be used in order to avoid congestion delays. In this paper, ant colony algorithms were used to find and optimize routes in a mesh-based NoC, where several randomly generated applications have been mapped. The routing optimization is driven by the minimization of total latency in packets transmission between tasks. The simulation results show the effectiveness of the ant colony inspired routing by comparing it with general purpose algorithms for deadlock free routing. © 2012 Springer-Verlag.

关键词： Ant colony optimization

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On the performance of STAR: an efficient delay-bound, low-cost multicast algorithm

On the performance of STAR: an efficient delay-bound, low-co...

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Annual Symposium on Simulation

作者： Shu Li R. Melhem T.F. Znati Department of Computer Science University of Pittsburgh Pittsburgh PA USA Department of Computer Science University of Pittsburgh Pittsburgh PA Telecommunications Program University of Pittsburgh Pittsburgh PA USA

Multicast networking is poised to play a prominent role in the future deployment of multimedia applications. Multimedia applications are usually resource intensive, have stringent quality of service requirements, and in many cases involve large multicast groups. Multicasting enables these applications to scale to a large number of users without overloading the network and server resources. This paper focuses on the design and analysis of a new heuristic for building low-cost, delay-bounded multicast trees to support multimedia applications. The approach used by the proposed heuristic to "optimize" the multicast tree limits its paths computation to paths which originate from the multicast destinations instead of all pairs of paths, as is the case in other well-known algorithms. Moreover, the path finding procedure, based on Dijkstra's algorithm, results in the selection of better paths than those discovered the k-shortest path based procedures. The simulation results show that the proposed heuristic outperforms on average other known heuristics.

关键词： Delay Multicast algorithms Application software Quality of service Routing Algorithm design and analysis Bandwidth Buildings Computational modeling Jitter

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A massively parallel hardware architecture for ray-tracing

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International Journal of High Performance Systems Architecture 2009年第1期2卷 26-34页

作者： Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil

Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Ray tracing

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Systems for spectrum forensics 2

Systems for spectrum forensics

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2nd ACM International Workshop on Hot Topics in Wireless, HotWireless 2015

作者： Anderson, Austin Wang, Xiang Baker, Kenneth R. Grunwald, Dirk Dept. of Aerospace Engineering Univ. of Colorado Boulder United States Dept. of Electrical Energy and Computer Engineering Univ. of Colorado Boulder United States Interdisciplinary Telecommunications Program Univ. of Colorado Boulder United States Dept. of Computer Science Univ. of Colorado Boulder United States

ISBN: (纸本)9781450336994

Historically, spectrum allocations were assigned to a single user by regulation and spectrum interference was relatively easy to identify. Enforcement was simplified by having a small set of known licensees. Spectrum regulation is increasingly moving toward dynamic spectrum access mediated by databases, exclusion zones, sensors and other methods intended to improve spectrum efficiency. To have meaning, these spectrum sharing mechanisms must have some form of enforcement. While the spectrum policy community has consider ex-post (preventative) and ex-ante (punitive) enforcement mechanisms, enforcement will rely on spectrum forensics - the scientific gathering of information to inform an enforcement action. In this paper, we initiate exploration of a system for spectrum forensics that combines crowd-sourced interference detection, fixed sensors and aerial measurement as well as a system for minimizing the data that needs to be collected. As part of a multi-tiered approach, the highest tier will be enabled by the equivalent of an "SDR in the sky" for self-directed localization and identification of interference sources.

关键词： Antennas

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An efficient parallel architecture for ray-tracing

An efficient parallel architecture for ray-tracing

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作者： Nery, Alexandre S. Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microeletronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro RJ Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade Do Estado Do Rio de Janeiro Rio de Janeiro RJ Brazil

Real time rendering of three-dimensional scenes in high photorealistic details is a hard task, such as in the ray tracing rendering algorithm. In general, the performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. However, parallel implementations of ray tracing have been enabling reasonable real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an even higher performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of ray tracing, such as shadows and reflection effects, imposing low area cost and a promising rendering performance. Such architecture, called GridRT, is based on the Uniform Grid acceleration structure and is intended to deliver massive parallelism through parallel ray-triangle intersection tests as well as parallel processing of many rays. A hardware implementation of the proposed architecture is presented, together with some performance results and resources requirements. The rendering is reduced by 80% using a grid configuration of eight processing elements. © Springer science+Business Media, LLC 2011.

关键词： Field programmable gate arrays (FPGA)

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A performance study of a highly-parallel architecture to provide registration and translation services in an intelligent network 92

A performance study of a highly-parallel architecture to pro...

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Proceedings of the 1992 ACM annual conference on Communications

作者： Jerry Stach Jerry Place Computer Science Telecommunications program University of Mo. - Kansas City 5100 Rockhill Rd. Kansas City MO

ISBN: (纸本)9780897914727

This paper presents the initial investigation of a highly parallel architecture that can be used as an Intelligent Network Translation and Registration Platform (INTARP). The INTARP architecture is deterministic and uses a hyper-switch as well as bus connections to pass messages. Threads through the multiprocessing pipelines are maintained by service definitions of the call procedures on “anchor processors”. The processes call procedures distributed over “sequencing processors”. INTARP is being prototyped using the inMOS, family of transputers. Unlike other architectures designed for the Intelligent Network, INTARP is designed specifically to minimize the post dial delay (PDD) the architecture contributes to circuit switch call processing. Unmanaged PDD in the Intelligent Network can lead to higher call abandonments. PDD also increase trunk and port capitalization due to the greater call holding time in peripheral processors prior to information transfer. The INTARP architecture is evaluated using a simulation model. Translation, PCN Registration and Calling Card services have been implemented on the simulation model and the performance of the architecture is inferred from the performance of the simulation studies.

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A j-bit bus architecture for multimedia local ATM network (MLAN)

A j-bit bus architecture for multimedia local ATM network (M...

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MILCOM, Military Communications Conference

作者： U. Varshney J.P. Agrawal Computer Information Sciences Washburn University Topeka KS USA Computer Science Telecommunications Program University of Missouri Kansas City Kansas City MO USA

With the emerging multimedia services, there is a need to support these services in the local area environment. In the last few years, many LAN protocols have been proposed or modified to fulfill this need. One such protocol is multimedia local ATM network (MLAN) protocol that is based on the bidirectional broadcast bus topology. The MLAN, suitable for campus environment, operates in the native ATM mode and does dynamic and fair bandwidth allocation to service multimedia traffic, and, offers connectionless as well as connection oriented service for MLAN-ATM network communication. From the previously published performance results, it is clear that MLAN provides excellent performance for distances from 1 to 3 km. To support applications requiring longer distances, we propose a new j-bit bus architecture for MLAN protocol. In this architecture, a terminal does not require j separate interfaces but is attached to the j-bit bus using one parallel interface. With the j-bit bus architecture, the MLAN can be extended to many times of the original coverage, depending upon the value of j employed. The MLAN protocol's performance has been determined by computer simulation using a multimedia traffic model. Based on the results, the proposed j-bit bus MLAN architecture is well suited for designing high speed multimedia ATM LANs.

关键词： Protocols computer architecture Local area networks Digital multimedia broadcasting Multimedia communication Network topology Channel allocation Telecommunication traffic computer simulation Traffic control

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Achieving compelling student comprehension of complex information structures for both on-site and on-line courses

Achieving compelling student comprehension of complex inform...

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2008 ASEE Annual Conference and Exposition

作者： Uhlig, Ronald Farahani, Alireza Viswanathan, Shekar Evans, Howard Sotelo, Mark National University Department of Computer Science and Information Systems School of Engineering and Technology National University Wireless Communications for the Master ot Science in Wireless Communications Program International Telecommunications Academy School of Engineering and Technology Department of Applied Engineering Lead Faculty for Engineering Management and Homeland Security and Safety Engineering Academic Computing for National University

Teaching engineering and technology subjects involves conveying understanding of abstract information structures and processes such as complex telecommunications protocols, complex mathematical concepts, and data structures. These are multidimensional and can be difficult to grasp quickly. Supported by a Hewlett-Packard (HP) Technology for Teaching grant, the School of Engineering and Technology at National University has embarked on a project to enable students to grasp these complex concepts more quickly and easily, using continuous dialog among students and instructors as the structures are first introduced and then examined from multiple perspectives through real-time interaction among students, small groups, and instructors. HP Wireless Tablet PCs are used to discuss and experiment with diagrams and processes in realtime. This allows combining lectures and problem-solving sessions into a single class session. Our hypothesis is that: 1) an in-depth learning of theory is accomplished, and 2) student engagement is enhanced. Presentation of theory by the instructor is integrated with application while the theory is still in the student's short-term memory. Students no longer have to wait for a separate session such as a recitation session to apply the concepts. This approach often takes less time. In addition to accelerating the learning process, expert instructors find this approach more rewarding as students grasp new concepts more quickly. Analysis of data captured from both students and instructors are presented to support our hypotheses, and our results are compared with similar research carried out by other universities. In addition, the level of interaction enabled by the use of HP Tablets in on-line classes is discussed. The best teaching tools available in existing on-line teaching platforms are compared with the additional tools available in on-site courses when every student has a wireless Tablet PC and specific recommendations are made to on-line teachi

关键词： Students

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A linear algebraic approach to queueing theory

A linear algebraic approach to queueing theory

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Symposium on Applied Computing

作者： L.R. Lipsky A. van de Liefvoort Department of Computer Science and Engr Booth Research Center University of Connecticut Storrs CT USA Computer Science Telecommunications Program University of Missouri Kansas City Kansas City MO USA

A survey of the basic formulas of queueing theory is presented, indicating their limitations in dealing with non-exponential service time distributions and non-steady-state behavior. The authors then describe a linear algebraic formulation which is a complete procedure for dealing with non-exponential servers. The formulation is invariant to a class of similarity transformations and thus does not depend on the phases used to describe the servers. The authors show how to treat M/G/1, G/M/1 and G/G/1 queues using this formalism. Finally, they show how transient properties of queueing systems can be calculated, using the same mathematical objects which were used for analyzing their steady-state properties.< >

关键词： Queueing analysis computer science Steady-state Time measurement Distributed computing Numerical stability Cities and towns Transient analysis

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