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Multi-Photon Tolerant Secure Quantum Communication - From Theory to Practice

Multi-Photon Tolerant Secure Quantum Communication - From Th...

引用

IEEE International Conference on Communications

作者： Yuhua Chen Subhash Kak Pramode K. Verma Gregory Macdonald Mayssaa El Rifai Nikhil Punekar Dept. of Electrical and Computer Engineering University of Houston Houston TX USA Department of Computer Science Oklahoma State University Stillwater OK USA Telecommunications Engineering Program University of Oklahoma-Tulsa Tulsa OK USA

Contemporary implementations of Quantum Key Distribution are based on BB84, first proposed in 1984, and commercially implemented for limited market applications in the early 2000 s. A major limitation of BB84 is that it requires no more than a single photon per time slot. But no device can reliably generate single photons with guaranteed periodicity. In this paper, we address the practical issues of realizing quantum cryptography systems. In particular, we address the major shortcomings of quantum cryptography as practiced today - the limitation of requiring a single photon to be used in communication. This not only affects the security of the practical quantum cryptography systems, but also restricts the distance over which secure keys can be sent and their rate. Our approach is not limited to a single photon per time-slot thus making it possible to send keys faster and over longer distances. The paper discusses the innate nature of multi-photon communication protocols as a surrogate for quantum communication while giving it a cryptographic strength that would closely match that of a pure quantum communication system.

关键词： Photonics Protocols Cryptography Laser beams Quantum mechanics

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Performance of redundancy methods in P2P networks under churn

Performance of redundancy methods in P2P networks under chur...

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2012 International Conference on Computing, Networking and Communications, ICNC'12

作者： Herrera-Ruiz, Octavio Znati, Taieb Graduate Telecommunications Program School of Information Science United States Computer Science Department School of Arts and Sciences University of Pittsburgh United States

ISBN: (纸本)9781467300094

Peer-to-Peer (P2P) networks organize large amounts of resources distributed across the Internet for user access. However, the availability of these resources is hindered by the participants' transient connectivity. Redundancy can be used to deal with this problem, but the redundancy repair traffic must be controlled to prevent performance degradation. In this paper, we present a comprehensive analytical formulation for erasure code redundancy methods in P2P networks, focused on fragments availability and redundancy repair cost. We use this model to evaluate the effectiveness of a proposed new redundancy scheme (PR) that outperforms other methods. Our results provide important insights for the design and construction of automated content availability mechanisms for P2P overlays under churn. Our evaluation framework allows us to determine at which point substituting a traditional erasure coding method (MDS) with other schemes is viable. For instance, e-MBR network coding performs worst than MDS for average fragment availabilities below 0.52. In addition, our experimental results indicate that adaptive repair strategies with elastic maintenance intervals can produce significant bandwidth savings compared with reactive and periodic redundancy repair strategies. In our experimental evaluation, an adaptive repair strategy consumes up to 49% less bandwidth than its periodic counterpart. © 2012 IEEE.

关键词： Redundancy

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Proactive repair redundancy algorithms for distributed storage in P2P networks

Proactive repair redundancy algorithms for distributed stora...

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2012 26th Queen's Biennial Symposium on Communications, QBSC 2012

作者： Herrera, Octavio Znati, Taieb Graduate Telecommunications Program School of Information Science United States Computer Science Department School of Arts and Sciences University of Pittsburgh United States

ISBN: (纸本)9781467311137

Distributed storage systems frequently use erasure coding based redundancy or replication to improve availability. Traditional erasure coding based approaches to redundancy are optimal in terms of their storage overhead-reliability tradeoff, but are expensive to repair. In this paper, we propose Proactive Repair (PR), a novel hybrid redundancy scheme. We discuss the implementation of the proposed scheme and discuss an emulated-based experimental study to evaluate PR's performance. The results show that PR outperforms exact-repair Minimum Bandwidth Regenerating (exact-MBR) network coding in terms of complexity and repair traffic overhead. Content availability when the system uses PR exhibits higher ability to dynamically adapt to changing failures rates, caused by nodes leaving the network. © 2012 IEEE.

关键词： Redundancy

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Static packet routing in NoC platform using ACO-based algorithms

Static packet routing in NoC platform using ACO-based algori...

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13th International Conference on Intelligent Data Engineering and Automated Learning, IDEAL 2012

作者： Silva Jr., Luneque Nedjah, Nadia De Macedo Mourelle, Luiza Systems Engineering and Computer Science Program COPPE Federal University of Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications State University of Rio de Janeiro Brazil Department of Systems Engineering and Computation State University of Rio de Janeiro Brazil

ISBN: (纸本)9783642326387

Networks-on-Chip (NoC) have been used as an interesting option in design of communication infrastructures for embedded systems, providing a scalable structure and balancing the communication between cores. Because several data packets can be transmitted simultaneously through the network, an efficient routing strategy must be used in order to avoid congestion delays. In this paper, ant colony algorithms were used to find and optimize routes in a mesh-based NoC, where several randomly generated applications have been mapped. The routing optimization is driven by the minimization of total latency in packets transmission between tasks. The simulation results show the effectiveness of the ant colony inspired routing by comparing it with general purpose algorithms for deadlock free routing. © 2012 Springer-Verlag.

关键词： Ant colony optimization

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An efficient parallel architecture for ray-tracing

An efficient parallel architecture for ray-tracing

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作者： Nery, Alexandre S. Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microeletronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro RJ Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade Do Estado Do Rio de Janeiro Rio de Janeiro RJ Brazil

Real time rendering of three-dimensional scenes in high photorealistic details is a hard task, such as in the ray tracing rendering algorithm. In general, the performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. However, parallel implementations of ray tracing have been enabling reasonable real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an even higher performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of ray tracing, such as shadows and reflection effects, imposing low area cost and a promising rendering performance. Such architecture, called GridRT, is based on the Uniform Grid acceleration structure and is intended to deliver massive parallelism through parallel ray-triangle intersection tests as well as parallel processing of many rays. A hardware implementation of the proposed architecture is presented, together with some performance results and resources requirements. The rendering is reduced by 80% using a grid configuration of eight processing elements. © Springer science+Business Media, LLC 2011.

关键词： Field programmable gate arrays (FPGA)

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization program processors Adders Delay

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Sensing as a service: An exploration into practical implementations of DSA

Sensing as a service: An exploration into practical implemen...

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2010 IEEE Symposium on New Frontiers in Dynamic Spectrum, DySPAN 2010

作者： Weiss, Martin B. H. Delaere, Simon Lehr, William H. Telecommunications Program School of Information Sciences University of Pittsburgh Pittsburgh PA 15260 United States IBBT-SMIT Vrije Universiteit Brussel Belgium Laboratory for Computer Science Massachusetts Institute of Technology United States

ISBN: (纸本)9781424451883

The cognitive radio literature generally assumes that the functions required for non-cooperative secondary DSA are integrated into a single radio system. It need not be so. In this paper, we model cognitive radio functions as a value chain and explore the implications of different forms of organization of this value chain. We initially explore the consequences of separating the sensing function from other cognitive radio functions. ©2010 IEEE.

关键词： Cognitive radio

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