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Thermomechanical reliability of high density wiring substrates

Thermomechanical reliability of high density wiring substrat...

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Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： S. Hedge R.V. Pucha A. Takahashi N. Takano S.K. Sitaraman George W. Woodruff Sch. of Mech. Eng. Georgia Inst. of Technol. Atlanta GA USA Computer Aided Simulation of Packaging Reliability (CASPaR) Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA Computer Aided Simulation of Packaging Reliability (CASPaR) Laboratory Georgia Institute of Technology Atlanta GA Hitachi Chemical Co. Ltd Japan Hitachi Chemical Co. Ltd Atlanta Japan

The thermomechanical response of multi-layered high density wiring (HDW) substrates is influenced by various material and geometrical parameters. This study aims at understanding the role and interaction of various dielectric and base substrate materials on different failure mechanisms. Experimental thermals cycling results are presented and the failure modes observed in test samples are discussed. Nonlinear finite element models are developed to estimate the warpage of the substrate, stresses in the dielectric layer and solder bump strains. The input factors for the analysis are grouped under material properties and geometry, and a selection technique is used to identify important factors. Based on the study, a response surface is generated to understand the role and interaction of input parameters on various failure mechanisms, and such a response surface will be used to tailor material properties for the High Density Wiring (HDW) structures.

关键词： Thermomechanical processes Wiring Dielectric substrates Dielectric materials Failure analysis Material properties Response surface methodology Testing Finite element methods Thermal stresses

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Modeling and simulation of hybrid dynamical systems with generalized differential Petri nets

Modeling and simulation of hybrid dynamical systems with gen...

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IEEE International Symposium on Intelligent Control (ISIC)

作者： Yali Wu Weimin Wu Jianchao Zeng Guoji Sun Hongye Su Jian Chu System Engineering Institute Xi''an Jiaotong University Xi'an China Institute of Advanced Process Control National Laboratory of Industrial Control Technology Zhejiang University Hangzhou China Division of System Simulation and Computer Application Taipan Heavy Machinery Institute Taipan China

There has been considerable interest in the modeling and simulation of hybrid dynamic systems (HDS). As an effective modeling tool of discrete event dynamic systems, Petri nets have a dual nature of a graphical tool and a mathematical object. In this paper, an extension of Petri net named generalized differential Petri nets (GDPN) is proposed to model HDS that have a combination of discrete-event evolution and continuous state evolution. Differential place and differential transition defined by Demongodin et al. (1998) are used to model the numeral simulation of the continuous dynamic process, and the weights defined on the directed arcs that connects the differential transitions and places are extended from real numbers to real matrices. The marking of differential place are also enlarged from real numbers to real vectors. Then the evolution rules and modeling method of HDS with GDPN are introduced. Two examples are used to illustrate the modeling power of GDPN in HDS.

关键词： Petri nets Power system modeling Supervisory control Discrete event systems Process control Computational modeling computer simulation Mathematical model Chemical processes Continuous time systems

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Coupled thermal electric-modeling of flexible nanospring interconnects for high-performance probing

Coupled thermal electric-modeling of flexible nanospring int...

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Electronic Components and technology Conference (ECTC)

作者： M. Ahmad S.K. Sitaraman Computer-Aided Simulation of Packaging Reliability Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)0780370384

Advances in integrated circuit fabrication have given rise to a need for an innovative, inexpensive, yet reliable probing technology with ultra-fine pitch capability. Research teams at Georgia Tech, Xerox PARC, and Nanonexus, Inc. Are developing flexible nanospring structures that can far exceed the probing needs of the next-generation microelectronic devices. Highly compliant cantilevered springs have been fabricated at pitches as small as 6 /spl mu/m. These nanosprings are designed to accommodate topological variation in probing surfaces while flexing within the elastic regime. For both probing and packaging applications, these nanosprings will service as current carriers and will heat up as a result of Joule heating. In probing applications, a current of about 200 mA is passed through these probes. Due to their extremely small dimensions, the electrical resistance of-these nanosprings will be higher than in conventional probes. Moreover, the existence of a sharp tip implies very high current densities at the spring tip. This, in turn, could result in higher temperatures at the spring tip. These higher temperatures could be detrimental to the reliability of the wafer that is being probed. It is important to determine the maximum temperature reached during probing, and how that, maximum temperature could be reduced. Coupled thermal-electric finite element models have been developed to understand the thermal contours developed across these springs, and to determine the maximum temperature reached. The current density through the nanospring is determined through an electrical model, and temperature contours are determined from the coupled electro-thermal model. The magnitude and the location of the maximum temperature depends on the spring geometry and the spring tip-bonding pad interface. Optimization of the spring geometry to reduce this maximum temperature is outlined. The role of depth of penetration in the bonding pad, on the maximum temperature and the electric

关键词： Couplings Springs Electric resistance Probes Current density Temperature dependence Geometry Conducting materials Thermal conductivity Thermal resistance

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Selection of base substrate material for design against interfacial delamination for a multilayered system-on-package (SOP) structure

Selection of base substrate material for design against inte...

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Electronic Components and technology Conference (ECTC)

作者： Weidong Xie Hurang Hu S.K. Sitaraman Computer-Aided Simulation of Packaging Reliability CASPaR Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA Department of Engineering Clark Atlanta University Atlanta GA USA

ISBN: (纸本)0780370384

System-On-Package (SOP) can reduce package size, increase functionality and improve performance at lower costs by embedding passives in a multilayered high-density wiring (HDW) structure. Due to the stringent warpage requirement for processing such a package, new base substrate materials are being explored with high modulus. The substrate will also have a CTE that is close to that of the die. The matched CTE will facilitate no-underfill attach flip-chips on SOP substrates. One major concern with the high-modulus "matched" CTE substrate is the potential interfacial delamination between different dielectric and metallization layers built-up on top of the base substrate. This research examines the possibilities of interfacial delamination in such a multilayered packaging structure under thermal loading. The objective of this paper is to evaluate the possibility of interfacial delamination of the new SOP integrated substrates with a primary focus on metallization copper and dielectric layer interface. An analytical model and numerical model have been developed to calculate the energy release rate of multilayered structures under thermal load. Based on the analysis results, a base layer material has been selected from a group of candidate materials. With this material as the base layer, the substrate has the minimum chance for a delamination to grow. The interfacial fracture toughness of copper/ViaLux/sup TM/ 81 PDDF has been measured. The energy release rate obtained from the analysis was compared with the interfacial fracture toughness, and the results indicate that there is minimal delamination growth under the given thermal load conditions. Based on analysis results, design recommendations for improving thermomechanical reliability are proposed.

关键词： Dielectric substrates Delamination Dielectric materials Packaging Thermal loading Metallization Copper Cost function Wiring Analytical models

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Compliant cantilevered spring interconnects for flip-chip packaging

Compliant cantilevered spring interconnects for flip-chip pa...

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Electronic Components and technology Conference (ECTC)

作者： Lunyu Ma Qi Zhu S.K. Sitaraman C. Chua D.K. Fork Computer-Aided Simulation of Packaging Reliability CASPaR Laboratory The Georgia W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA Xerox Palo Alto Research Center Palo Alto CA USA

ISBN: (纸本)0780370384

A new highly-compliant cantilevered spring interconnect is being developed to enable a fine-pitch, high density I/O architecture for the next generation chip and probing technology. This technology meets the requirements of National technology Roadmap for Semiconductor (NTRS) for 2012 and beyond. Based on its unique structure, a new contact mode - sliding contact with no solder is being tested. To understand the reliability of the package with this novel compliant spring interconnect structure and the typical behavior of the sliding contact, test vehicles with different orientations of the cantilevered springs (21 /spl mu/m pitch) have been fabricated, assembled and subjected to thermal cycling test. In-situ resistance and temperature measurements have been conducted. Material characterization of underfill has also been conducted.

关键词： Springs Packaging Testing Fabrication Sputtering Compressive stress Vehicles Argon Tensile stress Assembly

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Novel nanospring interconnects for high-density applications

Novel nanospring interconnects for high-density applications

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International Symposium on Advanced Packaging Materials

作者： Lunyu Ma Qi Zhu S.K. Sitaraman C. Chua D.K. Fork Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory The Georgia W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA Xerox Palo Alto Research Center Palo Alto CA USA

ISBN: (纸本)0930815645

A new cantilevered structure, called the nanospring, is being developed to enable a fine-pitch, high density I/O architecture for the next generation chip and probing technology. This technology meets the requirements of the National technology Roadmap for Semiconductors (NTRS) for 2012 and beyond. Based on its unique structure, a new contact mode of sliding contact with no solder is being tested. To understand the reliability of the package with this novel compliant structure and the typical behavior of sliding contacts, test vehicles with different orientations of the nanospring (21 /spl mu/m pitch) have been fabricated, assembled and subjected to thermal cycling tests. In-situ resistance and temperature measurements have been conducted.

关键词： Testing Tensile stress Fabrication Vehicles Electronic packaging thermal management Thermal stresses Compressive stress Application software Nanostructures Costs

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Qualification guidelines for automotive packaging devices

Qualification guidelines for automotive packaging devices

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Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： R. Raghunathan S.K. Sitaraman Computer-Aided Simulation of Packaging Reliability Laboratory The George W Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

With the continued demand for miniaturization, with the advent of new materials and processes, and with increased demand for better performance and lower cost, reliability of microelectronic devices continues to be a major concern. As microelectronic packages are used in a wide range of applications from automotive to aerospace to telecommunications to biomedical devices, there is a need for developing suitable qualification standards for these application domains. The ongoing work at Georgia Tech aims to develop a comprehensive virtual qualification system taking into consideration the process mechanics of substrate fabrication and component assembly, time- and temperature-dependent material behavior, process-induced defects, and critical geometric features of the assembly. The objective of this paper is to present one such virtual qualification technique for microelectronic packages used in automotive applications. Numerical models have been developed that take into account the creep behavior of the solder joints, the viscoelastic behavior of the underfill and the temperature-dependent orthotropic properties of the substrate. The models account for the solder reflow process and underfill cure process. They also account for multiple reflow and burn-in testing of the devices. Based on the information collected in terms of weather, underhood conditions, and driving profiles, qualification temperature cycling guidelines have been developed for automotive devices. The possibility of backside die cracking due to tensile stresses has also been investigated. The results from the models are being compared against experimental data from in-house as well as industrial sources.

关键词： Qualifications Guidelines Automotive engineering Packaging Aerospace materials Microelectronics Biological materials Biomedical materials Assembly systems Semiconductor device modeling

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Analytical model to study interfacial delamination propagation in a multi-layered electronic packaging structure under thermal loading

Analytical model to study interfacial delamination propagati...

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Electronic Components and technology Conference (ECTC)

作者： H. Hu W. Xie S. Sitaraman Computer-Aided Simulation of Packaging Reliability Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

Single Level Integrated Module (SLIM) is a next-generation electronic packaging module that has the potential for high performance, low cost and small size. The proposed SLIM structure is a multi-layered structure with embedded passive layers in addition to signal, ground and power planes. At fabrication, assembly and different field conditions, significant interfacial stresses could develop due to the mismatch of the Coefficient of Thermal Expansion (CTE) among its different material systems. One of the most common failure modes in such a multi-layered structure is interfacial delamination. The objective of this research is to examine the possibilities of interfacial delamination in this multi-layered structure under thermal loading. A sophisticated analytical model has been developed in this work to determine energy release rate and stress intensity factor for delamination propagation. The model takes into consideration the temperature-dependent material properties as well as orthotropic material properties. Although delamination between two adjacent layers is studied, the model takes into consideration the effect of all dielectric, metallization, and substrate layers. Assuming that an initial delamination exists between the base layer and the metallization Copper layer, this work studies the propagation of delamination. In the analytical model, the base layer is modeled as an orthotropic thermoelastic material. Copper and the polymer dielectric material are modeled as isotropic elastic material. For the Copper/base layer interface, the variation of bimaterial constant (/spl epsi/) with temperature is obtained through the analytical model. The effect of some key parameters, such as the base layer material, the interlayer dielectric material, the metallization layer material, the base layer thickness, and the temperature range, etc. on energy release rate and fracture mode ratio is presented. Design recommendations for improved thermomechanical reliability are prop

关键词： Analytical models Delamination Dielectric materials Thermal stresses Metallization Copper Material properties Dielectric substrates Inorganic materials Electronics packaging

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Numerical study of interfacial delamination in a system-on-package (SOP) integrated substrate under thermal loading

Numerical study of interfacial delamination in a system-on-p...

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Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： W. Xie S.K. Sitaraman Computer-Aided Simulation of packaging Reliability (CASPaR) Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

Research on system-on-package (SOP) with integrated substrate is being pursued at Georgia Tech. The integrated substrate contains embedded thin-film passive components in a multilayered substrate to achieve higher performance, lower cost, smaller size and lighter weight. However, as in all multilayered structures, SOP integrated substrate could have higher interfacial stresses and therefore could have interfacial delamination induced by material properties mismatch under thermal loading, if not carefully designed and fabricated. In this study, numerical analyses have been performed to investigate interfacial delamination propagation in SOP integrated substrate under thermal loading. Three candidate base layer materials and two dielectric layer materials have been studied. Recommendations for reducing delamination propagation were suggested. Further study is being conducted to investigate effects of time and temperature dependent material properties and cyclic thermal loading conditions.

关键词： Delamination Thermal loading Thermal stresses Material properties Dielectric substrates Conducting materials Dielectric materials Transistors Costs Numerical analysis

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Does underfilling enhance BGA reliability?

Does underfilling enhance BGA reliability?

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Electronics Packaging technology Conference (EPTC)

作者： J. Pyland R. Pucha S. Sitaram Computer-Aided Simulation of Packaging Reliability CASPaR Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA Georgia Institute of Technology Atlanta GA US

ISBN: (纸本)0780366441

The effect of underfill on various thermomechanical reliability issues in SBGA (super ball grid array) packages is studied in this paper. Nonlinear finite element models with underfill and no-underfill have been developed, taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled as temperature and direction-dependent, as appropriate. The stress/strain variations in solder joints due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The possibility of delamination at the interposer-underfill interface and at the board-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA solder balls.

关键词： Capacitive sensors Residual stresses Thermal stresses Thermomechanical processes Electronics packaging Finite element methods Temperature Soldering Plastics Creep

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