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All Optical Cross-Connect system Using Erbium-Doped Fiber-Based Optical Switching Unit

All Optical Cross-Connect System Using Erbium-Doped Fiber-Ba...

引用

20th Congress of the International Commission for Optics

作者： Chien-Hung Yeh Chien-Chung Lee Sien Chib Transmission System Dept. Computer & Communications Research Laboratories Industrial Technology Research Institute Rm. 143 Bldg. 14 195 Sec. 4 Chung Hsing Rd. Chutung Hsinchu 310 Taiwan R.O.C Department of Photonics & Institute of Electro-Optical Engineering National Chiao Tung University Hsinchu 310 Taiwan R.O.C. Department of Photonics & Institute of Electro-Optical Engineering National Chiao Tung University Hsinchu 310 Taiwan R.O.C. Department of Electrical Engineering Yuan Ze University Chung-Li 320 Taiwan R.O.C.

A novel bidirectional 2×2 optical switch technique, based on the conventional erbium-doped fibers (EDFs) with an operation of pumped or unpumped power level, is proposed and demonstrated experimentall

关键词： EDF, optical switching, cross connect

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AN adaptive DSP processor for high-efficiency computing MPEG-4 video encoder

AN adaptive DSP processor for high-efficiency computing MPEG...

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2004 IEEE International Symposium on Circuits and systems - Proceedings

作者： Chen, Li-Hsun Chen, Oscal T.-C. Wang, Teng-Yi Wang, Chi-Lung Signal and Media Laboratories Department of Electrical Engineering National Chung Cheng University Chia-Yi 621 Taiwan Computer System Development Dept. Comp./Communications Research Labs. Indust. Technol. Research Institute Hsinchu 310 Taiwan

An adaptive Digital Signal Processor (DSP) is proposed to realize the MPEG-4 video encoder at a high ratio of computation power versus hardware cost. First, software analyses are performed on the MPEG-4 video encoder, looking at the function and instruction levels. Analytical results from the function-level analysis show that the motion estimation inside the MPEG-4 video encoder has high computational complexity. As for the instruction-level analysis on the MPEG-4 video encoder without motion estimation, results reveal that the DSP equipped with 5 Arithmetic Logic Units (ALUs), 1 multiplier and 2 Load/Store units has the highest computation performance than the other architectures with 8 functional units. Furthermore, the design of the adaptive mechanism could be incorporated in the said functional units. The suggestion would be to group 4 ALUs and a multiplier into a special functional unit, to process exclusively motion estimation. With the fact that a multiplier can be constructed by using multiple adders, the adaptable structure is also designed so that the numbers of adders and multipliers required can be dynamically changed to increase parallelism capability of local instructions, especially in discrete cosine transform and inverse discrete cosine transform. In comparing to the conventional DSPs, the proposed adaptive DSP shows the best ratio of computation power over hardware cost to realize the MPEG-4 video encoder.

关键词： Digital signal processing

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An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder

An adaptive DSP processor for high-efficiency computing MPEG...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Li-Hsun Chen O.T.-C. Chen Teng-Yi Wang Chi-Lung Wang Signal and Media Laboratories Department of Electrical Engineering National Chung Cheng University Chiayi Taiwan Computer System Development Department Computer & Communications Research Laboratories Industrial Technology and Research Institute Hsinchu Taiwan

An adaptive digital signal processor (DSP) is proposed to realize the MPEG-4 video encoder at a high ratio of computation power versus hardware cost. First, software analyses are performed on the MPEG-4 video encoder, looking at the function and instruction levels. Analytical results from the function-level analysis show that the motion estimation inside the MPEG-4 video encoder has high computational complexity. As for the instruction-level analysis on the MPEG-4 video encoder without motion estimation, results reveal that the DSP equipped with 5 arithmetic logic units (ALUs), 1 multiplier and 2 Load/Store units has a higher computation performance than the other architectures with 8 functional units. Furthermore, the design of the adaptive mechanism can be incorporated in the said functional units. The suggestion is to group 4 ALUs and a multiplier into a special functional unit to exclusively process motion estimation. With the fact that a multiplier can be constructed by using multiple adders, the adaptable structure is also designed so that the numbers of adders and multipliers required can be dynamically changed to increase parallelism capability of local instructions, especially in discrete cosine transform and inverse discrete cosine transform. In comparing to conventional DSPs, the proposed adaptive DSP shows the best ratio of computation power over hardware cost to realize the MPEG-4 video encoder.

关键词： Digital signal processing MPEG 4 Standard Motion estimation Hardware Costs Performance analysis Discrete cosine transforms Digital signal processors Software performance Computational complexity

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A low-complexity architecture of inverse fast Fourier transform for XDS

A low-complexity architecture of inverse fast Fourier transf...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Hsin-Horng Chen O.T.-C. Chen Heng-Cheng Yeh Cheng-Shing Wu Signal and Media Laboratories Department of Electrical Engineering National Chung Cheng University Chiayi Taiwan Transmission System Department Computer & Communications Research Laboratories Industrial Technology and Research Institute Hsinchu Taiwan

In this work, a low-complexity architecture of the inverse fast Fourier transform (IFFT) using the serial-input-parallel-output data flow is designed for digital subscriber line for any class (XDSL). Since input data in the XDSL are symmetric, the computation of the IFFT can be reduced to multiplication accumulation operations in the real part. Furthermore, consideration is taken to process all multiplication operations together to lower hardware complexity. By separating all multiplication and accumulation operations into two groups, only an interface is needed to be the bridge between the two. The coefficients of the IFFT are represented by the canonic signed digits (CSDs) so that their shared terms are derived to reduce the number of adders for accomplishing multiplication operations. By using multiplexors to do the interface, the computation results from the multiplication part are distributed to their corresponding accumulators according to a time sequence. In addition, the size of the word length can be adequately selected to match the required signal-to-noise ratio (SNR). As compared to the conventional IFFT architectures, the proposed IFFT architecture can have the least hardware complexity at the same throughput rate and SNR performance.

关键词： Fast Fourier transforms Hardware Signal processing Concurrent computing computer architecture Discrete Fourier transforms Discrete cosine transforms Bridges Throughput OFDM modulation

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Differentiated-service enabled group communications using bandwidth brokers

Differentiated-service enabled group communications using ba...

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IEEE International Conference on Performance, Computing and communications (IPCCC)

作者： M. Goel M. Moh T. Hasegawa S. Ano Department of Computer Science San Jose State University Foundation San Jose CA USA KDDI Research & Development Laboratories Network Management System Saitama Japan

This paper addresses the challenge of providing scalable end-to-end differentiated service for group communications. While bandwidth broker (BB) has been proposed for guaranteed services in unicasting, no work has been done to extend it for multicasting. We propose a single-layer BB architecture for intra-domain multicast, and a multi-layer BB for end-to-end services across multiple network domains. Databases in the BB, the join and leave procedures, and their associated control messages are carefully designed. Complexities of the two proposed architectures are formally analyzed. It is shown that, comparing with the single-layer BB architecture, the multi-layer architecture results in much lower join costs and control-message complexity, and is thus highly scalable. Performance is evaluated via simulation of a multi-domain network with heterogeneous receivers. The proposed multi-layer BB architecture successfully provides end-to-end service differentiation in terms of throughput, end-to-end delay, and packet losses. We believe that this work is significant towards offering end-to-end differentiated-service group communications in large-scaled networks.

关键词： Bandwidth Quality of service Telecommunication traffic Traffic control Diffserv networks Databases computer science Costs Communication system control Throughput

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Acoustic tracking of sperm whales using two sets of hydrophone array

Acoustic tracking of sperm whales using two sets of hydropho...

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International Symposium on Underwater Technology

作者： T. Ura R. Bahl M. Sakata J. Kojima T. Fukuchi J. Ura Y. Nose H. Sugimatsu K. Mori T. Nakatani M. Yanagisawa Underwater Technology Research Center Institute of Industrial Science University of Tokyo Meguro Tokyo Japan KDD Research and Development Laboratories Inc. Kamifukuoka Saitama Japan System Giken Corporation Chigasaki Kanagawa Japan Department of Computer Engineering and Network Engineering Waseda University Tokyo Japan Ogasawara Whale Watching Association Chichijima Ogasawara Tokyo Japan Department of Computer Engineering and Network Engineering Waseda University Shinjuku Tokyo Japan

Sperm whales are known to dive to a depth of over two thousand meters and it is also known that they emit loud impulsive broadband sounds called "clicks" during their diving. However, little is known about sperm whales' behavior because of a shortage of methods to observe them during their dives. Our attempt is to use the autonomous underwater vehicle (AUV) as an observation platform for sperm whales. The tasks of AUV are to recognize sperm whales individually and track them in real time by listening to sperm whale's clicks with 4-hydrophone array and detecting its direction. As the initial stage for these objectives, we set up an experiment for our observation system using a boat instead of AUV and a support boat. In the middle of August 2003, we carried out an experiment to test our observation system off Ogasawara Islands. Two boats, each with a hydrophone array were deployed mainly in the west or southeast of Chichijima Island in an ocean depth of about 1000 meters. During the experiments over five days we encountered at least fourteen sperm whales. The result of this experiment indicates that our observation system is suitable for tracking sperm whales in sub-real time. We also acquired sufficient sound data of sperm whale's vocalization for off-line verification. The analysis of the results is presently underway. This experiment can be considered as the preliminary step to apply this kind of technique to develop innovative observation for underwater ecosystem system using AUVs.

关键词： Whales Sonar equipment Acoustic arrays Underwater tracking Boats Underwater acoustics Acoustical engineering Underwater vehicles system testing Oceans

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development of AUV-based system for acoustic tracking of diving sperm whales

Development of AUV-based system for acoustic tracking of div...

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OCEANS

作者： T. Ura R. Bahl M. Sakata J. Kojima T. Fukuchi J. Ura K. Mori T. Nakatani Y. Nose H. Sugimatsu Underwater Technology Research Center Institute of Industrial Science University of Tokyo Meguro Tokyo Japan KDD Research and Development Laboratories Inc. Kamifukuoka Saitama Japan System Giken Corporation Chigasaki Kanagawa Japan Department of Computer Engineering and Network Engineering Waseda University Shinjuku Tokyo Japan Ogasawara Whale Watching Association Chichijima Ogasawara Tokyo Japan

Sperm whales are known to dive to a depth of over two thousand meters. They emit loud impulsive broadband sounds called "clicks" during their diving. To investigate the sperm whale behavior, we attempt to apply the autonomous underwater vehicle (AUV) as an observation platform for sperm whales. AUV recognizes sperm whales individually and tracks them by listening to their clicks. As an initial stage for these objectives, we set up an experiment to test our observation system using two boats without an AUV. The observation system consists of two sets of 4-hydrophone arrays. Each hydrophone array works as a short baseline (SBL) system. The SBL system detects sperm whale clicks and calculates the orientation to sperm whales. Two relative directions from the two SBL arrays separated over a long base line (LBL) tell us the position of whale by triangulation. In the middle of August 2003, we carried out an experiment of the test system off Chichijima Island in Ogasawara. We deployed two boats each with a hydrophone array. An acoustic link between the SBL arrays was established to obtain the LBL length. During the experiments over five days we encountered at least fourteen sperm whales and succeeded in tracking some sperm whales by our observation system. Later in September 2004, we will perform another experiment using an AUV that works as one of the SBL systems. We expect this AUV-based observation system will give us a better understanding of sperm whale diving behavior and eco-system

关键词： Whales Sonar equipment Boats Underwater tracking system testing Acoustical engineering Underwater vehicles Acoustic arrays Humans Sea surface

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A high-efficiency reconfigurable digital signal processor for multimedia computing

A high-efficiency reconfigurable digital signal processor fo...

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Proceedings of the 2003 IEEE International Symposium on Circuits and systems

作者： Chen, Li-Hsun Chen, Oscal T.-C. Ma, Ruey-Liang Signal and Media Laboratories Department of Electrical Engineering National Chung Cheng University Chia-Yi 621 Taiwan Computer System Development Dept. Comp./Communications Research Labs. Indust. Technol. Research Institute Hsinchu 310 Taiwan

In this work, a high-efficiency reconfigurable digital signal processor (DSP) that consists of two arithmetic logic units and a reconfigurable computation unit is designed. The design methodology for the reconfigurable computation unit is explored based on the intermediate grain framework. The proposed reconfigurable computation unit includes 8×8 array processing elements and interconnection paths where the processing element is based on two 8-bit ripple adders and simple logic gates. This reconfigurable computation unit can be configured to perform special operations such as two 16×16-bit multiplication, sixteen 32-bit addition/subtraction, one 16-bit dot product and sixteen 8-bit absolute that utilize these 64 processing elements in different connection topologies to increase their usage rates. In the benchmark analyses, the 8×8-pixel motion estimation and 8×8-pixel discrete cosine transform are realized in the proposed reconfigurable DSP, TI TMS320C64 and MorphoSys. Additionally, the comparison of computation performances and hardware costs is performed to show that the proposed reconfigurable DSP is able to achieve a higher computation performance at a low hardware cost. Therefore, the reconfigurable DSP proposed herein can achieve high-efficiency computing for various multimedia applications.

关键词： Digital signal processing

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A high-efficiency reconfigurable digital signal processor for multimedia computing

A high-efficiency reconfigurable digital signal processor fo...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Li-Hsun Chen O.T.-C. Chen Ruey-Ling Ma Signal and Media Laboratories Department of Electrical Engineering National Chung Cheng University Chiayi Taiwan Computer System Development Department Computer & Communications Research Laboratories Industrial Technology and Research Institute Hsinchu Taiwan

In this work, a high-efficiency reconfigurable digital signal processor (DSP) that consists of two arithmetic logic units and a reconfigurable computation unit is designed. The design methodology for the reconfigurable computation unit is explored based on the intermediate grain framework. The proposed reconfigurable computation unit includes 8/spl times/8 array processing elements and interconnection paths where the processing element is based on two 8-bit ripple adders and simple logic gates. This reconfigurable computation unit can be configured to perform special operations such as two 16/spl times/16-bit multiplication, sixteen 32-bit addition/subtraction, one 16-bit dot product and sixteen 8-bit absolute that utilize these 64 processing elements in different connection topologies to increase their usage rates. In the benchmark analyses, the 8/spl times/8-pixel motion estimation and 8/spl times/8-pixel discrete cosine transform are realized in the proposed reconfigurable DSP, TI TMS320C64 and MorphoSys. Additionally, the comparison of computation performances and hardware costs is performed to show that the proposed reconfigurable DSP is able to achieve a higher computation performance at a low hardware cost. Therefore, the reconfigurable DSP proposed herein can achieve high-efficiency computing for various multimedia applications.

关键词： Digital signal processors Multimedia computing Digital signal processing Reconfigurable logic High performance computing Hardware Costs Digital arithmetic Logic design Signal design

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An XML-based context-aware transformation framework for mobile execution environments

An XML-based context-aware transformation framework for mobi...

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5th Asia-Pacific Web Conference, APWeb 2003

作者： Kao, Tzu-Han Shen, Sheng-Po Yuan, Shyan-Ming Cheng, Po-Wen Department of Computer and Information Science National Chiao Tung University 1001 Ta Hsueh Rd Hsinchu300 Taiwan Internet System Technology Department Computer and Communications Research Laboratories Industrial Technology Research Institute 195 sec. 4 Chung Hsing Rd Chutung Hsinchu310 Taiwan

ISBN: (纸本)9783540023548

We propose an XML-based Context-Aware transformation Framework (X-CAF). In X-CAF, we design three main techniques - (1) an XMLbased programming model to program applications, (2) a user interface adaptation mechanism to adjust UIs of applications, and (3) a transformation scheme to transform programs adapt to various MExE environments. Moreover, we design two methods, Static-time Component Generation and Runtime XUL Transformation for transforming efficiently and flexibility. Through applying these techniques, this framework may make applications device-independent. © Springer-Verlag Berlin Heidelberg 2003.

关键词： XML

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