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Definition of evaluation criteria for system development acquisition modeling and simulation

NAVAL ENGINEERS JOURNAL 1999年第1期111卷 55-64页

作者： Leite, MJ Mensh, DR Michael J. Leite:is a Principal Engineer with PRC Inc. a division of Litton Industries. He supports combat system engineering for theater air and missile defense. His other tasks have included the command and control for the AEGIS shipbuilding program systems engineering for the 21st Century Surface Combatant combat system survivability and the development of NATO standardization agreements for naval ordnance. He was previously a Senior Engineer with San Diego Gas & Electric with responsibility for its energy application and lighting programs. Prior to joining SDG&E Mr. Leite was a commissioned officer in the U.S. Navy where he served in operations and engineering assignments. Following active duty he accepted a Naval Reserve commission and has retired with the rank of Captain. His assignments included command operational and engineering tours. Mr. Leite has also served as an expert witness in admiralty and engineering matters. He is a gradate of the University of California Berkeley with a Bachelor of Science Degree in Engineering and also holds a Masters Degree in Business Administration from National University in San Diego. Mr. Leite is a Registered Professional Engineer in the States of California and Minnesota. Mr. Leite is a member of ASNE ASCE MORS the Illuminating Engineering Society and the U.S. Naval institute. Dennis Roy Mensh:is a Senior Engineer with PRC Inc. a division of Litton Industries in Crystal City VA where he supports modeling and simulation tasking for combat systems. He received BS and MS degrees in applied Physics from Lopola College in Baltimore MD and the American University in Washington DC. He has also completed the course work towards a Ph.D. degree in computer science specializing in the fields of Operations Reseurch Anabsis Systems Analysis and Computer Modeling and Simulation. Previously he was employed at the White Oak Laboratory of the Naval Surface Warfare Carter in Silver Spring MD where he worked in the areas of naval sensor and weapon system analysis

This paper defines, develops and examines a set of generic analysis tools that can be applied to Models and Simulations at the systems Engineering level of fidelity. The tools examine the performance and effectiveness of Sensors;Weapons;and Battle Management, Command, Control, Communications, computers, and Intelligence ((BMCI)-I-4) systems and equipment. The Measures of Performance (MOPs), Measures of Effectiveness (MOEs) and Measures of Force Effectiveness (MOFEs) were extracted from the Modular Command and Control Structure Paradigm which was developed at the Naval Postgraduate School. The paradigm provides for the development of evaluation criteria (MOPs, MOEs, and MOFEs) in a framework that ensures the traceability of system performance and effectiveness to the system operational requirements as specified in the Operational Requirements Document (ORD). Also, the analysis tools provide insight and valid estimates of numerical measures of the defined system functionality threads, which represent the system's operational requirements as specified in the ORD. The tools are directly transferrable and applicable to test and evaluation exercise events which are conducted in support of the development and acquisition of systems and equipment. Once the levels of system performance have been defined, the Paradigm generates a quantitative database that becomes a useful tool in system tradeoffs and selection. Once the alternative system suites have been defined, the suites can be analyzed in terms of system functionality threads and their corresponding performance capabilities versus cost.

关键词： Naval vessels

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Parallel scientific computing in promoter on the interface between application modelling and language design 98

Parallel scientific computing in promoter on the interface b...

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1998 ACM Symposium on Applied Computing, SAC 1998

作者： Besch, Matthias Heber, Gerd Wilhelmi, Matthias Parallel and Distributed Systems GMD Laboratory GMD-FIRST Rudower Chaussee 5 BerlinD-12489 Germany Computer Architecture and Parallel Systems Laboratory University of Delaware 140 Evans Hall NewarkDE19716 United States

ISBN: (纸本)0897919696

a key issue of problem-oriented parallel programming is an appropriate concept for representing the spatial structures of an application and modelling local or global interactions operating on them. This paper advocates for the use of so-called index spaces as a unified and powerful expression tool. It discusses the interface between application modelling and programming abstractions, and presents their embeddings in the high-level, data parallel language Promoter. © 1998 ACM.

关键词： Parallel programming

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The SAVANT project

The SAVANT project

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： P.A. Wilsey D.E. Martin H. Hirsch Computer Architecture Design Laboratory Department of ECECS University of Cincinnati Cincinnati OH USA MTL Systems Inc. Dayton OH USA

The SAVANT project is a joint program between the Air Force, MTL systems, Inc. and the University of Cincinnati to develop a VHDL analyzer that is freely redistributable for noncommercial use. The goal is to facilitate the insertion of VHDL technology into the government, industrial, and university research and development programs. The analyzer validates the correctness of the input VHDL and builds an intermediate representation in memory for manipulation by backend analysis tools (e.g., behavioral synthesis, fault modeling, and simulation code generators). The intermediate (called AIRE/CE) is well-documented, in review for standardization, and in use by other commercial vendors. The SAVANT technology is freely available in source code form and, under separate programs, the University of Cincinnati is also developing a backend code generator and simulation kernel so that complete front-to-back analysis and simulation activities can be performed with nearly free software.

关键词： Analytical models Object oriented modeling Performance analysis Contracts computer architecture Laboratories Plasma welding Research and development Standardization Kernel

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Effects of multithreading on data and workload distribution for distributed-memory multiprocessors

Effects of multithreading on data and workload distribution ...

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International Symposium on Parallel Processing

作者： A. Sohn M. Sato Namhoon Yoo J.-L. Gaudiot Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan Department of EE-Systems University of Southern California Los Angeles CA USA

While data and workload distribution can be tailored to fit a particular problem to a particular distributed-memory architecture, it is often difficult to do so for various practical issues. This paper presents our study on multithreading for distributed-memory multiprocessors. Specifically, we investigate the effects of multithreading on data distribution and workload distribution with variable thread granularity. Various types of workload distribution strategies are defined along thread granularity. Three types of data distribution strategies are investigated: row-wise cyclic, k-way partial-row cyclic and blocked distribution. We have implemented all of these on the 80-processor EM-4 distributed-memory multiprocessor using highly-sequential Gaussian elimination with partial pivoting and highly-parallel matrix multiplication. Experimental results indicated that multithreading can offset the loss that is due to the mismatch of data distribution to workload distribution for even sequential and irregular problems while giving high absolute performance.

关键词： Multithreading Yarn Distribution strategy Performance loss

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HP's PA7100LC: a low-cost superscalar PA-RISC processor

HP's PA7100LC: a low-cost superscalar PA-RISC processor

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IEEE Compcon

作者： P. Knebel B. Arnold M. Bass W. Kever J.D. Lamb R.B. Lee P.L. Perez S. Undy W. Walker Information Systems Laboratory Hewlett Packard Company Fort Collins CO USA Computer Systems Architecture Laboratory Cupertino CA USA

Describes a new low-cost, superscalar PA-RISC processor including two integer arithmetic and logic units, a floating-point coprocessor, and a memory and I/O controller on a single VLSI chip. It implements the full PA-RISC1.1 functionality and adds several new features, including little-endian capability, uncacheable memory pages, and new multimedia instructions. The chip is fabricated in 0.8- mu m, three-level metal CMOS and is designed to run from 0 to 75 MHz. The cache system consists of an off-chip combined instruction/data cache ranging from 8 kByte to 2 MByte and a small on-chip instruction buffer. Memory consists of 4 MByte to 2 GByte of standard DRAMs or SIMMs (single in-line memory modules) connecting directly to the processor chip. The chip achieves performance levels comparable to those of previous generation high-end workstations while lowering overall system cost and power consumption to make possible a new generation of low-cost systems.< >

关键词： Power generation Floating-point arithmetic CMOS logic circuits Coprocessors Very large scale integration System-on-a-chip Joining processes Workstations Costs Energy consumption

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Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors 93

Hardware/software resolution of pipeline hazards in pipeline...

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IEEE International Conference on computer-Aided Design

作者： I.-J. Huang A.M. Despain Advanced Computer Architecture Laboratory Department of Electrical Engineering-Systems University of Southern California USA

ISBN: (纸本)9780818644900

One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. We present a new solution to the problem in the domain of pipelined application-specific instruction set processors, based on hardware/software concurrent engineering approach. An extended taxonomy of inter-instruction dependencies is proposed for the analysis of pipeline hazards. Hardware/software resolution candidates are then associated with these dependencies. Algorithms using the taxonomy and the resolutions are developed to detect and resolve pipeline hazards, and to explore the hardware and software design space. Application benchmarks are used to evaluate the designs and guide the design decision. The power of these tools are demonstrated through the pipeline synthesis of two processors including industrial one. Compared with other approaches, our method achieves higher throughput, and provides a way to explore the hardware/software tradeoff. Our method can be combined with current approaches to achieve even higher performance since they are orthogonal.

关键词： Hardware Hazards Pipeline processing Taxonomy Delay Application software Throughput Space exploration computer architecture Laboratories

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PDAS: Processor design automation system

PDAS: Processor design automation system

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European Design Automation Conference

作者： I. Pyo A.M. Despain Advanced Computer Architecture Laboratory Department of Electrical Engineering-Systems University of Southern California USA

The PDAS (Processor Design Automation System) is a new approach to design automation that uses formal methods to achieve a new level of design power and the ability to formally validate designs. The idea is to develop a design automation system which considers both microprocessor hardware design and design of the corresponding language compiler concurrently. Benchmark programs are used to motivate design decisions and optimize performance. Compiler optimizations are considered during the design of hardware. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation.< >

关键词： Personal digital assistants Design automation Natural languages Specification languages Hardware Design optimization Process design Formal languages Concrete computer architecture

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A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus 26

A microarchitectural performance evaluation of a 3.2 Gbyte/s...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Tim Stanley Michael Upton Patrick Sherhart Trevor Mudge Richard Brown Advanced Computer Architecture Laboratory Department of Electrical Engineering-Systems University of Southern California USA Department of Electrical Computer Engineering Drexel University Philadelphia PA USA Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780818652806

The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined instruction set processors. However, it does not consider the relative spatial positions of micro-operations in the pipeline, thus providing limited hints to hardware designers and compiler writers about the hazard resolution in generalized pipeline structures. The authors propose an extension to the conventional classification of dependencies, which is capable of encapsulating the spatial/temporal relationship and providing precise hardware/software resolution strategies. With the extended classification and its associated hardware/software resolution strategies, they are able to systematically analyze the potential register-related pipeline hazards for a given pipeline structure, determine appropriate resolution strategies, and explore the tradeoff between hardware and software complexities. The methodology enables the systematic synthesis of high performance pipelined micro-architectures, and is useful to derive the back-end of the supporting compilers.< >

关键词： Hazards Pipeline processing Hardware Application software computer architecture Laboratories High level synthesis Design automation Throughput System performance

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Verification of self-checking properties by means of output code space computation

Verification of self-checking properties by means of output ...

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European Conference on Design Automation

作者： M. Nicolaidis M. Boudjit Reliable Integrated Systems Group Computer Architecture IMAG/TIMA Laboratory Grenoble France

In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of the system is intractable. The paper presents a tool which performs this computation with low CPU time. This tool is a part of PROTECT, a tool which is aimed at automatic generation of complex self-checking circuits.< >

关键词： Circuit faults Protection Hardware Circuit testing Electrical fault detection Fault detection Encoding computer architecture Central Processing Unit Programming

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Parallel language constructs for efficient parallel processing

Parallel language constructs for efficient parallel processi...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： R.M. Clapp T.N. Mudge Sequent Computer Systems Inc. Beaverton OR USA Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Proposes some basic language extensions to incorporate a parallel procedure model into the C programming language. In order to improve on other proposals, the authors set the goals of their design to attain increased efficiency, flexibility, and expressiveness, and to improve parallel program structure. They begin by discussing the motivation for these goals, and then present an overview of their proposed model for parallel procedures. They then describe the design of the run-time system that supports the parallel procedure model. A novel scheme for nesting parallel procedure contexts in multiple stack frames is included in the run-time system, thus eliminating the need for costly process control blocks. After describing the details of the language and run-time system design, the authors then present detailed performance data for two parallel programs using this system.< >

关键词： Parallel languages Parallel processing Runtime Yarn Concurrent computing computer languages Parallel programming Operating systems Process control Data engineering

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