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Adaptive resource allocation for streaming applications

Adaptive resource allocation for streaming applications

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International Conference on Embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Timon D. ter Braak Hermen A. Toersche André B. J. Kokkeler Gerard J. M. Smit Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Enschede Netherlands

Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time.

关键词： Hardware Routing Resource management Global Navigation Satellite systems Receivers Tiles Radio frequency

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Design and Implementation of MapReduce Using the PGAS Programming Model with UPC

Design and Implementation of MapReduce Using the PGAS Progra...

引用

International Conference on Parallel and Distributed systems (ICPADS)

作者： Carlos Teijeiro Guillermo L. Taboada Juan Tourino Ramon Doallo Computer Architecture Group Department of Electronics and Systems Facultade de Informatica University of A Coruña A Coruna Spain

MapReduce is a powerful tool for processing large data sets used by many applications running in distributed environments. However, despite the increasing number of computationally intensive problems that require low-latency communications, the adoption of MapReduce in High Performance Computing (HPC) is still emerging. Here languages based on the Partitioned Global Address Space (PGAS) programming model have shown to be a good choice for implementing parallel applications, in order to take advantage of the increasing number of cores per node and the programmability benefits achieved by their global memory view, such as the transparent access to remote data. This paper presents the first PGAS-based MapReduce implementation that uses the Unified Parallel C (UPC) language, which (1) obtains programmability benefits in parallel programming, (2) offers advanced configuration options to define a customized load distribution for different codes, and (3) overcomes performance penalties and bottlenecks that have traditionally prevented the deployment of MapReduce applications in HPC. The performance evaluation of representative applications on shared and distributed memory environments assesses the scalability of the presented MapReduce framework, confirming its suitability.

关键词： Instruction sets Electronics packaging Libraries Multicore processing Programming Java

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Functional Framework and Hardware Platform for Dependability Study in Short Range Wireless Embedded systems

Functional Framework and Hardware Platform for Dependability...

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IEEE International Mixed-Signals, Sensors, and systems Test Workshop, IMS3TW

作者： Benaouneur Senouci Anne-Johan Annema Mark Bentum Hans G. Kerkhoff Telecommunication Engineering Group Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group University of Twente Enschede Netherlands Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and at different abstractions levels. This paper presents a hardware platform for wireless system dependability analysis as an alternative for the time consuming global system simulation technique. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed methodology are two fold: first it takes care of the whole system (HW/SW part, mixed RF and wireless part) and second, the hardware platform enables to explore the application's reliability under real environmental conditions in order to study the effect of the environment threats on the system.

关键词： Wireless communication Hardware Reliability System-on-a-chip computer architecture Libraries Embedded systems

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Towards dependability-aware design of hardware systems using extended program state machines

Towards dependability-aware design of hardware systems using...

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2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORCW 2011

作者： Grüttner, Kim Herrholz, Andreas Kühne, Ulrich Große, Daniel Rettberg, Achim Nebel, Wolfgang Drechsler, Rolf OFFIS - Institute for Information Technology HW/SW Design Methodology Group Oldenburg Germany CoSynth GmbH and Co. KG Oldenburg Germany LSV ENS de Cachan Cachan France University of Bremen Group for Computer Architecture Bremen Germany Carl Von Ossietzky University Oldenburg Embedded Hardware/Software Systems Oldenburg Germany

ISBN: (纸本)9780769543772

Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has to change fundamentally. Therefore, we propose a dependability-aware design approach for hardware systems through integrating dependability into a state-of-the-art system-level design language. Our approach is based on SystemC and extends the Program State Machine model to explicitly observe, diagnose, and compensate faulty behavior. Different compensation mechanisms like run-time reconfiguration or mechanisms for error propagation can be used by the designer during refinement. They are controlled by a new exception-like mechanism. Furthermore, our approach aims to integrate functional verification as well as dependability verification with respect to given fault models. © 2011 IEEE.

关键词： Embedded systems

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Fast subgraph isomorphism detection for graph-based retrieval

Fast subgraph isomorphism detection for graph-based retrieva...

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19th International Conference on Case-Based Reasoning, ICCBR 2011

作者： Weber, Markus Langenhan, Christoph Roth-Berghofer, Thomas Liwicki, Marcus Dengel, Andreas Petzold, Frank GmbH Trippstadter Straße 122 67663 Kaiserslautern Germany Knowledge-Based Systems Group Department of Computer Science University of Kaiserslautern P.O. Box 3049 67653 Kaiserslautern Germany Department of Architectural Informatics Faculty of Architecture Technical University of Munich Arcisstrasse 21 80333 Munich Germany Explanation-aware Computing Systems Institute of Computer Science University of Hildesheim Marienburger Platz 22 31141 Hildesheim Germany

ISBN: (纸本)9783642232909

In this paper we present a method for a graph-based retrieval and its application in architectural floor plan retrieval. The proposed method is an extension of a well-known method for subgraph matching. This extension significantly reduces the storage amount and indexing time for graphs where the nodes are labeled with a rather small amount of different classes. In order to reduce the number of possible permutations, a weight function for labeled graphs is introduced and a well-founded total order is defined on the weights of the labels. Inversions which violate the order are not allowed. A computational complexity analysis of the new preprocessing is given and its completeness is proven. Furthermore, in a number of practical experiments with randomly generated graphs the improvement of the new approach is shown. In experiments performed on random sample graphs, the number of permutations has been decreased to a fraction of 10-18 in average compared to the original approach by Messmer. This makes indexing of larger graphs feasible, allowing for fast detection of subgraphs. © 2011 Springer-Verlag.

关键词： Graph theory

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Ensuring privacy in a Distributed Video Coding surveillance scenario

Ensuring privacy in a Distributed Video Coding surveillance ...

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1st IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2011

作者： Martínez, J.L. Villalón, J.M. Parreño, J.H. Cuenca, P. Kalva, H. Architecture and Technology of Computing Systems Group Complutense University Ciudad Universitaria s/n 28040 Madrid Spain University of Castilla-La Mancha Campus Universitario 02071 Albacete Spain Department of Computer Science and Engineering Florida Atlantic University 777 Glades Rd Boca Raton FL 34341 United States

ISBN: (纸本)9781457702341

In this paper, a permutation scheme is introduced for Distributed Video Coding. The main goal is to preserve privacy and security in video surveillance video communications and can be adapted for other scenarios. The proposed approach consists to apply permutation based encryption to the DVC scenario. The permutation is defined by a secret key which is required at the decoder for decompression providing security. Simulation results show that the reference architecture and the permutation-based proposed have similar rate distortion performance. © 2011 IEEE.

关键词： Cryptography

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Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?

Towards an ESL design framework for adaptive and fault-toler...

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2011 9th IEEE Symposium on Embedded systems for Real-Time Multimedia, ESTIMedia 2011

作者： Cannella, Emanuele Di Gregorio, Lorenzo Fiorin, Leandro Lindwer, Menno Melonr, Paolo Neugebauer, Olaf Pimentel, Andy Leiden Institute of Advanced Computer Science Leiden University Netherlands Lantiq Deutschland GmbH Neubiberg Germany ALaRI Faculty of Informatics University of Lugano Switzerland Silicon Hive BV High Tech Campus 83 5656 AG Eindhoven Netherlands DIEE Department of Electrical and Electronic Engineering University of Cagliari Cagliari Italy Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Computer Systems Architecture Group Informatics Institute University of Amsterdam Netherlands

ISBN: (纸本)9781457721236

The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods. © 2011 IEEE.

关键词： Middleware

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Job Scheduling with License Reservation: A Semantic Approach

Job Scheduling with License Reservation: A Semantic Approach

引用

Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： Jorge Ejarque Andras Micsik Raul Sirvent Peter Pallinger Laszlo Kovacs Rosa M. Badia Computer Architecture Department Universitat Politecnica de Catalunya Barcelona Spain Grid Computing and Clusters Group Barcelona Supercomputing Center Barcelona Spain Distributed Systems Department-Computer and Automation Research Institute Hungarian Academy of Sciences (ATOMKI) Budapest Hungary Artificial Intelligence Research Institute Spanish National Research Council Barcelona Spain

The license management is one of the main concerns when Independent Software Vendors (ISV) try to distribute their software in computing platforms such as Clouds. They want to be sure that customers use their software according to their license terms. The work presented in this paper tries to solve part of this problem extending a semantic resource allocation approach for supporting the scheduling of job taking into account software licenses. This approach defines the licenses as another type of computational resource which is available in the system and must be allocated to the different jobs requested by the users. License terms are modeled as resource properties, which describe the license constraints. A resource ontology has been extended in order to model the relations between customers, providers, jobs, resources and licenses in detail and make them machine processable. The license scheduling has been introduced in a semantic resource allocation process by providing a set of rules, which evaluate the semantic license terms during the job scheduling.

关键词： Licenses Software Semantics Resource management Ontologies Processor scheduling Law

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Towards Dependability-Aware Design of Hardware systems Using Extended Program State Machines

Towards Dependability-Aware Design of Hardware Systems Using...

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IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW)

作者： Kim Gruttner Andreas Herrholz Ulrich Kuhne Daniel Grosse Achim Rettberg Wolfgang Nebel Rolf Drechsler HW/SW Design Methodology Group OFFIS Institute of Information Technology Oldenburg Germany CoSynth GmbH and Company KG Oldenburg Germany LSV ENS de Cachan Cachan France Group for Computer Architecture University of Brethemen Bremen Germany Embedded Hardware/Software Systems Carl von Ossietzky University슠of슠Oldenburg Oldenburg Germany

关键词： Computational modeling Hardware Circuit faults computer architecture Fault tolerance Switches Adaptation model

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Runtime task mapping based on hardware configuration reuse

Runtime task mapping based on hardware configuration reuse

引用

International Conference on Reconfigurable Computing and FPGAs

作者： Sigdel, Kamana Galuzzi, Carlo Bertels, Koen Thompson, Mark Pimentel, Andy D. Computer Engineering Group TU Delft Netherlands Systems Architecture Group UvA Netherlands

ISBN: (纸本)9780769543147

In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on hardware configuration reuse, which tries to avoid the reconfiguration overhead of few selected tasks, by reusing the hardware configurations already available in the reconfigurable hardware. We evaluate our heuristic by performing a mapping of an extended Motion-JPEG application onto a reconfigurable architecture. A large variety of experiments have been conducted on the proposed algorithm for the same reconfigurable architecture model with different FPGA sizes. The obtained result shows up to 45% performance gain by reusing the hardware configurations as suggested by the proposed heuristic, compared to well-known approaches from the state-of-the-art, which do not take into consideration the hardware configuration reuse. © 2010 IEEE.

关键词： Reconfigurable architectures

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