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Euromicro Symposium on Digital System Design

作者： Saman Froehlich Rolf Drechsler Group of Computer Architecture University of Bremen Germany Cyber-Physical Systems DFKI GmbH Germany

ISBN: (数字)9781665474047

ISBN: (纸本)9781665474054

In order to overcome the von Neumann bottleneck, recently the paradigm of in-memory computing has emerged. Here, instead of transferring data from the memory to the CPU for computation, the computation is directly performed within the memory. ReRAM, a resistance-based storage device, is a promising technology for this paradigm. Based on ReRAM, the PLiM computer architecture and LiM-HDL, an HDL for specifying PLiM programs have emerged. In this paper, we first present a novel levelization algorithm for LiM-HDL. Based on this novel algorithm, large circuits can be compiled to PLiM programs. Then, we present a verification scheme for these programs. This scheme is separated into two steps: (1) A proof of purity and (2) a proof of equivalence. Finally, in the experiments, we first apply our levelization algorithms to a well-known benchmark set, where we show that we can generate PLiM programs for large benchmarks, for which existing levelization algorithms fails. Then, we apply our proposed verification scheme to these PLiM programs.

关键词： Performance evaluation Digital systems computer architecture Benchmark testing In-memory computing Central Processing Unit Hardware design languages

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VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

VRank: Enhancing Verilog Code Generation from Large Language...

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IEEE International Symposium on Quality Electronic Design

作者： Zhuorui Zhao Ruidi Qiu Ing-Chao Lin Grace Li Zhang Bing Li Ulf Schlichtmann Chair of Electronic Design Automation Technical University of Munich (TUM) Munich Germany Computer Architecture and IC Design National Cheng Kung University Hardware for Artificial Intelligence Group Technical University of Darmstadt Research Group of Digital Integrated Systems University of Siegen

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes, previous methods require either time-consuming manual inspection or generation of multiple Verilog codes, from which the one with the highest quality is selected with manually designed testbenches. To enhance the generation efficiency while maintaining the quality of the generated codes, we propose VRank, an automatic framework that generates Verilog codes with LLMs. In our framework, multiple code candidates are generated with LLMs by leveraging their probabilistic nature. Afterwards, we group Verilog code candidates into clusters based on identical outputs when tested against the same testbench, which is also generated by LLMs. Clusters are ranked based on the consistency they show on testbench. To determine the best candidate, Chain-of-Thought is further applied to select the best candidate from the top-ranked clusters. By systematically analyzing diverse outputs of generated codes, VRank reduces errors and enhances the overall quality of the generated Verilog code. Experimental results on the VerilogEval-Human benchmark demonstrate a significant 10.5% average increase in functional correctness (pass@1) across multiple LLMs, demonstrating VRank's effectiveness in improving the accuracy of automated hardware description language generation for complex design tasks.

关键词： Codes Accuracy Large language models Manuals Inspection Probabilistic logic Hardware Cognition Reliability Hardware design languages

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Symbolic Fault Injection for Plan-based Robotics

Symbolic Fault Injection for Plan-based Robotics

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International Conference on Control, Automation and systems ( ICCAS)

作者： Tim Meywerk Vladimir Herdt Rolf Drechsler Group of Computer Architecture University of Bremen Bremen Germany Cyber-Physical Systems DFKI GmbH Bremen Germany

Autonomous robots are being used increasingly in safety-critical environments. Due to their dynamic nature and uncertainty, failures of low-level actions are common. In plan-based robotics, these failures are handled inside the higher-level plans, using a multitude of failure handling strategies. With the increasing complexity of robotic plans, failures may be accidentally left unhandled. This will usually stop the plan entirely. To avoid such a situation, the failure handling should ideally be complete, i.e. there should be no failure that can reach the top-level of the execution. In this paper, we propose to use formal methods, in particular symbolic fault injection to tackle the problem of finding unhandled failures or proving that no such failure exists. We implement symbolic fault injection for the CRAM Planning Language (CPL). We base our work on the worst-case assumption that any low-level action may fail at any time with any of its possible types of failure. Our work builds upon an existing symbolic execution engine for CPL and extends it to reason about CPL’s failure handling mechanism. We also present a way to implement the worst-case assumption directly into CPL. Our experimental evaluation suggests that symbolic fault injection is a suitable and scalable method to find unhandled failures in robotic plans.

关键词： Uncertainty Runtime Manuals Control systems Complexity theory Planning Flow graphs

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Assessing architecture Conformance to Security-Related Practices in Infrastructure as Code Based Deployments

Assessing Architecture Conformance to Security-Related Pract...

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IEEE International Conference on Services Computing (SCC)

作者： Evangelos Ntentos Uwe Zdun Ghareeb Falazi Uwe Breitenbü cher Frank Leymann Faculty of Computer Science Research Group Software Architecture University of Vienna Vienna Austria Institute of Architecture of Application Systems University of Stuttgart Stuttgart Germany

ISBN: (数字)9781665481465

ISBN: (纸本)9781665481472

Infrastructure as Code (IaC) enables developers and operations teams to automatically deploy and manage an IT infrastructure via software. Among other uses, IaC is widely used in the context of continuously released deployments such as those of microservice and other cloud-based systems. Although IaC-based deployments have been utilized by many companies, there are no approaches on checking their conformance to architectural aspects yet. In this paper, we focus on security-related practices including observability, access control, and traffic control in IaC-based deployments. While best practices for this topic have been documented in some gray literature sources such as practitioners’ blogs and public repositories, approaches enabling automated checking of conformance to such best practices do not yet exist. We propose a model-based approach based on generic, technology-independent metrics, tied to typical architectural design decisions on IaC-based deployments. With this approach, we can measure conformance to security-related practices. We demonstrate and assess the validity and appropriateness of these metrics in assessing a system’s conformance to practices through regression analysis.

关键词： Measurement Codes Service computing Microservice architectures computer architecture Traffic control Software

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Efficient machine learning through evolving combined deep neural networks 20

Efficient machine learning through evolving combined deep ne...

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2020 Genetic and Evolutionary Computation Conference, GECCO 2020

作者： Krauss, Rune Merten, Marcel Bockholt, Mirco Froehlich, Saman Drechsler, Rolf Cyber-Physical Systems DFKI GmbH and Group of Computer Architecture University of Bremen Germany

ISBN: (纸本)9781450371278

The usage of Artificial Neural Networks (ANNs) with a fixed topology is becoming more popular in daily life. However, there are problems where it is difficult to build an ANN manually. Therefore, genetic algorithms like NeuroEvolution of Augmented Topologies (NEAT) have been developed to find topologies and weights. The downside of NEAT is that it often generates inefficient large ANNs for different problems. In this paper, we introduce an approach called Turbo NEAT, which combines divide and conquer methods with NEAT to allow a symbiosis of specialised smaller ANNs. In addition, we optimise the weights of the ANNs through backpropagation in order to better compare the topologies. Experiments on several problems show that these approaches allow the handling of complex problems and lead to efficient ANNs. © 2020 Owner/Author.

关键词： Topology

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On Unifying the Compliance Management of Applications Based on IaC Automation

On Unifying the Compliance Management of Applications Based ...

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IEEE International Conference on Software architecture Workshops (ICSAW)

作者： Ghareeb Falazi Uwe Breitenbü cher Frank Leymann Miles Stö tzner Evangelos Ntentos Uwe Zdun Martin Becker Elena Heldwein Institute of Architecture of Application Systems University of Stuttgart Stuttgart Germany Research Group Software Architecture Faculty of Computer Science University of Vienna Vienna Austria IBM Deutschland B&#x00F6 blingen Germany

Infrastructure-as-Code (IaC) technologies are used to automate the deployment of cloud applications. They promote the usage of code to define and configure the IT infrastructure of cloud applications allowing them to benefit from conventional software development practices, which facilitates the rapid deployment of new versions of application infrastructures without sacrificing quality or stability. On the other hand, enterprise applications need to conform to compliance regarding external regulations and internal policies. Many of these compliance rules affect the application architecture on which IaC code operates. However, managing the architectural compliance of IaC-based application deployments faces a number of challenges, such as configuration drift and the heterogeneity of IaC technologies. Therefore, in this work, we present a vision on how to uniformly manage the compliance of the infrastructure of applications that utilize heterogeneous IaC technologies for deployment automation. To this end, we introduce an initial design for the IaC-based Architectural Compliance Management Framework and discuss how it addresses the corresponding challenges.

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Simulation-Based Debugging of Formal Environment Models*

Simulation-Based Debugging of Formal Environment Models*

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Mediterranean Conference on Control and Automation (MED)

作者： Tim Meywerk Arthur Niedzwiecki Vladimir Herdt Rolf Drechsler Research Group of Computer Architecture University of Bremen Germany Institute for Artificial Intelligence University of Bremen Germany Cyber Physical Systems DFKI GmbH Bremen Germany

ISBN: (数字)9781665406734

ISBN: (纸本)9781665406741

Logic-based formal models of robot environments are often used to aid the generation and verification of robotic plans. They are however often simplified and rather abstract compared to the real world that the robot acts in. This can lead to considerable discrepancies between the behavior of the formal model and that of physics-based simulation engines. These discrepancies are not always apparent to the designer. In this paper we propose a new methodology to make these discrepancies explicit by combining formal verification and simulation. Our approach is able to find relevant discrepancies, while only requiring a small number of simulations.

关键词： Automation Debugging Cognition Robots Engines Formal verification

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ALF - A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks

arXiv

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arXiv 2021年

作者： Krauss, Rune Merten, Marcel Bockholt, Mirco Drechsler, Rolf Group of Computer Architecture University of Bremen Germany Cyber-Physical Systems DFKI GmbH Germany

Machine Learning (ML) is becoming increasingly important in daily life. In this context, Artificial Neural Networks (ANNs) are a popular approach within ML methods to realize an artificial intelligence. Usually, the topology of ANNs is predetermined. However, there are problems where it is difficult to find a suitable topology. Therefore, Topology and Weight Evolving Artificial Neural Network (TWEANN) algorithms have been developed that can find ANN topologies and weights using genetic algorithms. A well-known downside for large-scale problems is that TWEANN algorithms often evolve inefficient ANNs and require long runtimes. To address this issue, we propose a new TWEANN algorithm called Artificial Life Form (ALF) with the following technical advancements: (1) speciation via structural and semantic similarity to form better candidate solutions, (2) dynamic adaptation of the observed candidate solutions for better convergence properties, and (3) integration of solution quality into genetic reproduction to increase the probability of optimization success. Experiments on large-scale ML problems confirm that these approaches allow the fast solving of these problems and lead to efficient evolved ANNs. Copyright © 2021, The Authors. All rights reserved.

关键词： Neural networks

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Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars

Automated Equivalence Checking Method for Majority based In-...

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Asia and South Pacific Design Automation Conference

作者： Arighna Deb Kamalika Datta Muhammad Hassan Saeideh Shirinzadeh Rolf Drechsler KIIT DU School of Electronics Engineering Bhubaneswar India German Research Centre for Artificial Intelligence (DPKI) Bremen Germany Fraunhofer Institute for Systems and Innovation-Research (ISI) Karlsruhe Germany Group of Computer Architecture University of Bremen Bremen Germany

Recent progress in the fabrication of Resistive Random Access Mem-ory (ReRAM) devices has paved the way for large scale crossbar structures. In particular, in-memory computing on ReRAM cross-bars helps in bridging the processor-memory speed gap for current CMOS technology. To this end, synthesis and mapping of Boolean functions to such crossbars have been investigated by researchers. However the verification of simple designs on crossbar is still done through manual inspection or sometimes complemented by sim-ulation based techniques. Clearly this is an important problem as real world designs are complex and have higher number of inputs. As a result manual inspection and simulation based methods for these designs are not practical. In this paper for the first time as per our knowledge we pro-pose an automated equivalence checking methodology for majority based in-memory designs on ReRAM crossbars. Our contributions are twofold: first, we introduce an intermediate data structure called ReRAM Sequence Graph (ReSG) to represent the logic-in-memory design. This in turn is translated into Boolean Satifiability (SAT) formulas. These SAT formulas are verified against the golden functional specification using Z3 Satifiability Modulo Theory (SMT) solver. We validate the proposed method by running widely avail-able benchmarks.

关键词： Fabrication Systematics Design automation Design methodology Manuals Inspection In-memory computing

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PROV-IO+: A Cross-Platform Provenance Framework for Scientific Data on HPC systems

arXiv

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arXiv 2023年

作者： Han, Runzhou Zheng, Mai Byna, Suren Tang, Houjun Dong, Bin Dai, Dong Chen, Yong Kim, Dongkyun Hassoun, Joseph Thorsley, David Wolf, Matthew Department of Electrical and Computer Engineering Iowa State University United States Department of Computer Science and Engineering The Ohio State University United States Scientific Data Management Group Lawrence Berkeley National Laboratory United States Computer Science Department University of North Carolina Charlotte United States Systems Architecture Lab Samsung United States Samsung Advanced Institute of Technology Samsung Korea Republic of

Data provenance, or data lineage, describes the life cycle of data. In scientific workflows on HPC systems, scientists often seek diverse provenance (e.g., origins of data products, usage patterns of datasets). Unfortunately, existing provenance solutions cannot address the challenges due to their incompatible provenance models and/or system implementations. In this paper, we analyze four representative scientific workflows in collaboration with the domain scientists to identify concrete provenance needs. Based on the first-hand analysis, we propose a provenance framework called PROV-IO+, which includes an I/O-centric provenance model for describing scientific data and the associated I/O operations and environments precisely. Moreover, we build a prototype of PROV-IO+ to enable end-to-end provenance support on real HPC systems with little manual effort. The PROV-IO+ framework can support both containerized and non-containerized workflows on different HPC platforms with flexibility in selecting various classes of provenance. Our experiments with realistic workflows show that PROV-IO+ can address the provenance needs of the domain scientists effectively with reasonable performance (e.g., less than 3.5% tracking overhead for most experiments). Moreover, PROV-IO+ outperforms a state-of-the-art system (i.e., ProvLake) in our experiments. © 2023, CC BY-NC-SA.

关键词： Life cycle

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