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Resource constrained modulo scheduling for coarse-grained reconfigurable arrays

Resource constrained modulo scheduling for coarse-grained re...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： G. Dimitroulakos M.D. Galanis C.E. Goutis VLSI Design Laboratory Electrical and Computer Engineering Department University of Patras Patras Greece

It is widely known that bandwidth limitations degrade parallel systems' performance. This paper presents a mapping methodology for coarse-grain reconfigurable arrays which alleviates the bandwidth bottleneck by exploiting the processing elements interconnection network for transferring values with data reuse opportunities. A novel mapping algorithm is also proposed that uses a resource-aware modulo scheduling technique. From the application of the proposed mapping approach, significant improvements in performance were achieved while we have also quantified these improvements in respect to crucial architecture parameters such as the memory latency and the register file size. For this reason, our methodology targets on a parametric architecture template which can model a large number of existing architectures of this kind

关键词： Bandwidth Delay Registers Reconfigurable architectures Phased arrays Costs Processor scheduling Very large scale integration Laboratories Concurrent computing

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design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic 06

Design flow for optimizing performance in processor systems ...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： M.D. Galanis G. Dimitroulakos C.E. Goutis VLSI Design Laboratory Electrical and Computer Engineering Department University of Patras Rio Greece

ISBN: (纸本)9781424400546

A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-dimensional array of processing elements. Performance is improved by accelerating critical software loops, called kernels, on the reconfigurable array. Basic steps of the design flow have been automated. A procedure for detecting critical loops in the input C code was developed, while a mapping technique for coarse grain reconfigurable arrays, based on software pipelining, was also devised. Analytical results derived from mapping five real-life DSP applications on eight different instances of a generic system architecture are presented. Large values of instructions per cycle were achieved on two reconfigurable arrays that resulted in high-performance kernel mapping. Additionally, by mapping critical code on the reconfigurable logic, speedups ranging from 1.27 to 3.18 relative to an all-processor execution were achieved

关键词： design optimization System-on-a-chip Reconfigurable logic Kernel Process design Logic arrays Acceleration Software performance Pipeline processing Digital signal processing

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Mapping DSP Applications on Processor/Coarse-Grain Reconfigurable Array Architectures

Mapping DSP Applications on Processor/Coarse-Grain Reconfigu...

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Proceedings of 2006 IEEE International Symposium on Circuits and systems,Volume 7

作者： Michalis D. Galanis Gregory Dimitroulakos Costas E. Goutis VLSI Design Laboratory Electrical and Computer Engineering Department University of Patras Patras Greece

Results from mapping five real-world DSP applications on a system-on-chip that incorporates coarse-grain reconfigurable hardware with an instruction-set processor is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A mapping method for improving application's performance by accelerating critical software parts, called kernels, on the Coarse-Grain Reconfigurable Array is proposed. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed. Important overall application speedups, clue to the kernels' acceleration, have been reported for the five applications. These overall performance improvements range from 1.27 to 3.07, with an average value of 2.16, relative to an all-software execution.

关键词： Digital signal processing Application software Kernel Reconfigurable logic Acceleration computer architecture System-on-a-chip Hardware Logic arrays Software performance

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Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures 06

Exploring the design space of an optimized compiler approach...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： G. Dimitroulakos M.D. Galanis C.E. Goutis VLSI Design Laboratory Electrical and Computer Engineering Department University of Patras Patras Greece

ISBN: (纸本)9781424400546

In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architecture. The processing elements' local register files and the processing elements' interconnection network is exploited for caching memory data values with data reuse opportunities. The data reused values are transferred through the processing elements' interconnection network hence, relieving the bus from the burden of transferring these values. A novel mapping algorithm is also proposed that uses a modulo scheduling technique. This algorithm targets on a flexible architecture template which permits experimental exploration over different architecture alternatives. The experimental results showed that the operation parallelism was significantly improved by our mapping approach. Additionally, we have outlined the relation that exists between the performance improvements and the memory access latency, the interconnection network and the processing elements' register file size.

关键词： Space exploration design optimization Optimizing compilers Reconfigurable architectures Parallel processing Registers Multiprocessor interconnection networks Scheduling Bandwidth computer architecture

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Improving Performance of Embedded Processors with a High-Performance Coarse-Grained Reconfigurable Data-Path

Improving Performance of Embedded Processors with a High-Per...

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Mediterranean Electrotechnical Conference (MELECON)

作者： M.D. Galanis G. Dimitroulakos C.E. Goutis VLSI Design Laboratory Electrical and Computer Engineering Department University of Patras Patras Greece

An embedded system that extends microprocessor cores with a high-performance coarse-grained reconfigurable data-path is introduced. The data-path is composed by computational resources able to realize complex operations which aid in improving the performance of time critical application parts, called kernels. A compilation flow is defined for mapping high-level software descriptions to the microprocessor system. The kernel code is mapped using a properly developed mapping algorithm for the reconfigurable data-path. Extensive exploration is performed by mapping four real-life applications on three different instances of the system. Important overall application speedups have been reported that range from 1.70 to 3.68 relative to an all-processor execution

关键词： Microprocessors Kernel Application software Reconfigurable logic Field programmable gate arrays Hardware Programmable logic arrays Embedded computing High performance computing Embedded system

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Transient event detection for nonintrusive load monitoring and demand side management using voltage distortion

Transient event detection for nonintrusive load monitoring a...

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21st Annual IEEE Applied Power Electronics Conference and Exposition, APEC '06

作者： Cox, Robert Leeb, Steven B. Shaw, Steven R. Norford, Leslie K. Laboratory for Electromagnetic and Electronic Systems Massachusetts Institute of Technology Cambridge MA 02139 Department of Electrical and Computer Engineering Montana State University Bozeman MT Department of Architecture Massachusetts Institute of Technology Cambridge MA 02139

ISBN: (纸本)0780395476

This paper describes a simple system that can be used for autonomous demand-side management in a load site such as a home or commercial facility. The system identifies the operation of individual loads using transient patterns observed in the voltage waveform measured at an electric service outlet. The theoretical foundation of the measurement process is introduced, and a preprocessor that computes short-time estimates of the spectral content of the voltage waveform is described. The paper presents several example measurements demonstrating the ability of the system to obtain estimates of the spectral content of the voltage waveform. © 2006 IEEE.

关键词： Electric loads

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VoMESH: voice over wireless MESH networks

VoMESH: voice over wireless MESH networks

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IEEE Conference on Wireless Communications and Networking

作者： Kyungtae Kim Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

In this work, we focus on increasing network utilization to support real-time applications, especially voice over IP, in 802.11b wireless mesh network. For increasing capacity, we investigate on two directions: use of packet aggregation and utilize of header compression. Although aggregation reduces 802.11 MAC overhead, it also increases delay. We present a distributed multihop aggregation algorithm that uses the "natural" waiting time in the interface queue of packets in a loaded network. Header compression can relax the VoIP protocol overhead, but it also introduces the signaling overhead. In our work, we propose a zero-length header compression algorithm integrated with packet aggregation, which doesn't need to depend on the signaling mechanism to recover the context discrepancy between compressor and decompressor. The above performance optimization techniques are experimented in the NS2 simulator. The experimental results show an increase of 12 times for a six hop string when all optimizations are used

关键词： Wireless mesh networks Internet telephony Protocols Mesh networks Costs Delay Spread spectrum communication Telecommunication traffic Traffic control Communication system security

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Guarantee of service expectation level and fairness by precise queue weight allocation in AF PHB

Guarantee of service expectation level and fairness by preci...

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IEEE Conference on Wireless Communications and Networking

作者： Sangkil Jung Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

Assured forwarding per-hop behavior (AF PHB) is a forwarding scheme for providing QoS in DiffServ networks. It defines four classes and three drop precedence, where buffer space and bandwidth are defined as forwarding resources for each AF class (J. Heinanen et al., 1999). RIO (D.D. Clark and W. Fang, 1998) could be used as drop policy in a DiffServ router. AF PHB could be implemented by WRR, WFQ, CBQ, etc. When network managers provide AF PHB using the scheduling mechanisms, they want to guarantee accurate achievement of service expectation level, which results from precise queue weight allocation to each AF class with respect to forwarding resources, i.e., buffer space and bandwidth. In order to provide a guideline for the precise queue weight allocation, this paper proposes a simple analytical model for AF PHB designed on RIO and M/M/1 queue, and uses this model to obtain queue weight equation (QWE), which performs fine calculation of queue weight for AF classes. Average buffer space and bandwidth allocated for each AF class are used in derivation of QWE. The model verification is performed by simulation in which we use WRR for simplicity. Simulation results show that the QWE supports an accurate allocation of the forwarding resources, and, as a result, makes four AF classes achieve fairness as well as service expectation levels

关键词： Bandwidth Queueing analysis Resource management Quality of service Diffserv networks Mobile computing Laboratories computer networks design engineering Guidelines

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Molecular incorporation of Saccharin into soft high moment CoFe alloys

Molecular incorporation of Saccharin into soft high moment C...

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9th International Symposium on Magnetic Materials, Processes and Devices - 210th ECS Meeting

作者： Brankovic, Stanko R. Haislmaeir, Ryan Vasiljevic, Natasa Electrical and Computer Engineering Department Center for Nanomagnetic Systems University of Houston Houston TX 77204-4005 United States Sandia National Laboratory Albuquerque NM 87185 United States Electrochemical Society

ISBN: (纸本)9781566775601

The incorporation of entire Saccharin molecules has been studied during the galvanostatic deposition of 2.45 T soft CoFe alloys. The results indicate that the incorporation rate of Saccharin molecules is strongly dependent on the concentration of this additive in the plating solution. This dependence shows a pronounced maximum at Csach = 0.12 g/lit, which is the result with significant practical implications. The simple physical model is developed to describe this dependence having an excellent qualitative prediction of the experimental data. The corrosion properties and surface roughness of 2.45 T CoFe alloys are found to be strong function of Saccharin concentration in the solution, i.e. Saccharin incorporation rate. copyright The Electrochemical Society.

关键词： Molecules

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Fault-Tolerant Scheduling of Independent Tasks in Computational Grid

Fault-Tolerant Scheduling of Independent Tasks in Computatio...

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International Conference on Communication systems

作者： Qin Zheng Bharadwaj Veeravalli Chen-khong Tham Computer Networks and Distributed Systems Laboratory (CNDS) Department of Electrical and Computer Engineering National University of Singapore Singapore

Primary-backup approach is a common approach used for fault tolerance wherein each task has a primary copy and a backup copy on two different processors. The backup copy can overlap with other backup copies on the same processor, as long as their corresponding primary copies are scheduled on different processors. In this paper, we consider the problem of fault-tolerant scheduling of independent tasks using primary-backup approach with backup overlapping in computational grid. A fault-tolerant scheduling algorithm is developed which minimizes replication cost for backup copy by taking into account backup overlapping in cost function. A centralized scheme and a distributed scheme are developed for the proposed algorithm and their performance are studied through simulation experiments

关键词： Fault tolerance Processor scheduling Grid computing Fault tolerant systems Cost function Distributed computing Scheduling algorithm computer networks Hardware Intelligent networks

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