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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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An estimation procedure to determine the effort required to model business processes

An estimation procedure to determine the effort required to ...

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作者： Cappelli, Claudia Santoro, Flávia Maria Nunes, Vanessa De Barros, Márcio O. Dutra, José Roberto Postgraduate Information Systems Program UNIRIO Av. Pasteur 458 Urca - Rio de Janeiro RJ Brazil COPPE/UFRJ Systems Engineering and Computer Science Program P.O. Box 68511 Rio de Janeiro RJ Brazil

ISBN: (纸本)9789898425065

Business processes modeling projects are increasingly widespread in organizations. Companies have several processes to be identified and modeled. They usually invest much in hiring expert consultants to do such job. However, they still find no guidelines to help them estimate how much a process modeling project will cost or how long this will take. We propose an approach to estimate the effort required to conduct a BPM project and discuss results obtained from over 50 projects in a large Brazilian company.

关键词： Process engineering

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Who is right? Evaluating empirical contradictions in the readability & comprehensibility of source code 20

Who is right? Evaluating empirical contradictions in the rea...

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20th Ibero-American Conference on Software engineering, CIbSE 2017

作者： Ribeiro, Talita Vieira Travassos, Guilherme Horta PESC/COPPE/UFRJ - Systems Engineering and Computer Science Program Centro de Tecnologia Federal University of Rio de Janeiro Cidade Universitária Bloco H Sala 319 Rio de Janeiro RJ Brazil

ISBN: (纸本)9789873806988

Context: Several code guidelines aim at providing a common perspective on the readability and comprehensibility of source code. However, in many cases, they are contradictory on how to improve these quality characteristics. Objective: To analyze the influence of three contradictory source code attributes - indentation spacing, identifier length and code size - on the source code reada-bility and comprehensibility, interpreting whether programming experience and domain knowledge can support explaining these contradictions. Method: To per-form an empirical study with software developers collecting quantitative (Likert scale) and qualitative data to assess the readability and comprehensibility of de-velopers regarding Python snippets. To observe eventual perceptions contradic-tions and whether their levels of experience and knowledge have something to do with such contrary results. Results: Regardless their programming experience, 4-spaces indentation dominated the readability preference of participants. While the readability and comprehensibility preferences towards long and complete-word identifiers were mostly true for both novice/experts, developers with more experience and low domain knowledge level seemed to be more affected by the length of identifiers. Furthermore, while all participants showed more positive comprehensibility perceptions for Pythin snippets with more lines of code, their readability perceptions regardnig code size were contradictory since the less experienced participants preferred more lines of code and the more experienced ones prefer fewer lines. Conclusion: The results presented in the technical literature seemed to be caused by the interchangeable use of the readability and comprehensibility concepts. Further investigation is still needed to observe whether other confounding factors might support the explanation of such contrary results.

关键词： Codes (symbols)

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An efficient parallel architecture for ray-tracing

An efficient parallel architecture for ray-tracing

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作者： Nery, Alexandre S. Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microeletronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro RJ Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade Do Estado Do Rio de Janeiro Rio de Janeiro RJ Brazil

Real time rendering of three-dimensional scenes in high photorealistic details is a hard task, such as in the ray tracing rendering algorithm. In general, the performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. However, parallel implementations of ray tracing have been enabling reasonable real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an even higher performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of ray tracing, such as shadows and reflection effects, imposing low area cost and a promising rendering performance. Such architecture, called GridRT, is based on the Uniform Grid acceleration structure and is intended to deliver massive parallelism through parallel ray-triangle intersection tests as well as parallel processing of many rays. A hardware implementation of the proposed architecture is presented, together with some performance results and resources requirements. The rendering is reduced by 80% using a grid configuration of eight processing elements. © Springer Science+Business Media, LLC 2011.

关键词： Field programmable gate arrays (FPGA)

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Logic as energy: A SAT-based approach

Logic as energy: A SAT-based approach

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2nd International Symposium on Brain, Vision, and Artificial Intelligence, BVAI 2007

作者： Lima, Priscila M. V. Morveli-Espinoza, M. Mariela M. França, Felipe M. G. LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal Do Rio de Janeiro Brazil Departament d'Informàtica Universitat Autònoma de Barcelona Spain COPPE - Systems Engineering and Computer Science Program Universidade Federal Do Rio de Janeiro Brazil

ISBN: (纸本)3540755543

This paper presents the implementation of ARQ-PROP II, a limited-depth propositional reasoner, via the compilation of its specification into an exact formulation using the satyrus platform. satyrus' compiler takes as input the definition of a problem as a set of pseudo-Boolean constraints and produces, as output, the Energy function of a higher-order artificial neural network. This way, satisfiability of a formula can be associated to global optima. In the case of ARQ-PROP II, global optima is associated to Resolution-based refutation, in such a way that allows for simplified abduction and prediction to be unified with deduction. Besides experimental results on deduction with ARQ-PROP II, this work also corrects the mapping of satisfiability into Energy minima originally proposed by Gadi Pinkas. © 2007 Springer-Verlag Berlin Heidelberg.

关键词： Neural networks

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Context-based process line

Context-based process line

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作者： Nunes, Vanessa Werner, Claudia Santoro, Flavia Maria COPPE/UFRJ Systems Engineering and Computer Science Program P.O. Box 68511 Rio de Janeiro RJ Brazil NP2Tec and Postgraduate Information Systems Program UNIRIO Av. Pasteur 458 Urca - Rio de Janeiro RJ Brazil

ISBN: (纸本)9789898425065

Complexity and dynamism of day-to-day activities in organizations are inextricably linked, one impacting the other, increasing the challenges for constant adaptation of the way to organize work to address emerging demands. In this scenario, there are a variety of information, insight and reasoning being processed between people and systems, during process execution. We argue that process variations could be decided in real time, using context information collected. This paper presents a proposal for a business process line cycle, with a set of activities encapsulated in the form of components as central artefact. We explain how composition and adaptation of work may occur in real time and discuss a scenario for this proposal.

关键词： Enterprise resource management

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Kairos: An Architecture for Securing Authorship and Temporal Information of Provenance Data in Grid-Enabled Workflow Management systems

Kairos: An Architecture for Securing Authorship and Temporal...

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IEEE International Conference on e-Science and Grid Computing

作者： Luiz M.R. Gadelha Jr Marta Mattoso Computer and Systems Engineering Program-COPPE Federal University of Rio de Janeiro Rio de Janeiro Brazil

Secure provenance techniques are essential in generating trustworthy provenance records, where one is interested in protecting their integrity, confidentiality, and availability. In this work, we suggest an architecture to provide protection of authorship and temporal information in grid-enabled provenance systems. It can be used in the resolution of conflicting intellectual property claims, and in the reliable chronological reconstitution of scientific experiments. We observe that some techniques from public key infrastructures can be readily applied for this purpose. We discuss the issues involved in the implementation of such architecture and describe some experiments realized with the proposed techniques.

关键词： Workflow management software Protection Data security Information security Intellectual property computer architecture Grid computing Digital signatures Distributed computing Mesh generation

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Rebuilding games at runtime

Rebuilding games at runtime

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IEEE/ACM International Conference on Automated Software engineering - Workshops (ASE Workshops)

作者： Diego Castro Cláudia Werner COPPE/Computer Systems Engineering Program Federal University of Rio de Janeiro Rio de Janeiro Brazil

ISBN: (纸本)9781665411851

The gaming industry is growing over time, having a considerable amount of fans. Creating a game is a complex process that can take a long time until its release, causing a lot of anxiety for the game fan population. Some of these fans can not wait for the release of a specific game, creating their own versions of games. This process of creating games in an ad-hoc manner from others that already exist is called mod and can be compared to the concept of Software Reuse, where software is created from others. This work aims to increase the systematic of creating mods based on reuse concepts such as Product Line. In this paper, an initial prototype of a game created by applying Product Line concepts to generate new mods in a more systematic way is described.

关键词： Industries Fans Systematics Runtime Conferences Sociology Prototypes

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SpMT WaveCache: Exploiting Thread-Level Parallelism in WaveScalar

SpMT WaveCache: Exploiting Thread-Level Parallelism in WaveS...

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computer Science and Information engineering, CSIE, WRI World Congress on FLAGGED

作者： Songwen Pei Baifeng Wu Min Du Gang Chen Leandro A.J. Marzulo Felipe M.G. Franca School of Computer Science Fudan University Shanghai China Systems Engineering and Computer Science Program COPPE Rio de Janeiro Brazil

Speculative multithreading (SpMT) increases the performance by means of executing multiple threads speculatively to exploit thread-level parallelism. By combining software and hardware approaches, we have improved the capabilities of previous WaveScalar ISA on the basis of transactional memory system for the WaveCache Architecture. Threads are extracted at the course of static compiling, and speculatively executed as a thread-level transaction that is supported by extra hardware components, such as thread-context-table (TCT) and thread-memory-history (TMH). We have evaluated the SpMT WaveCache with 6 real benchmarks from SPEC, Mediabench and Mibench. On the whole, the SpMT WaveCache outperforms superscalar architecture ranging from 2times to 3times, and great performance gains are achieved over original WaveCache and transactional WaveCache as well.

关键词： Yarn Parallel processing Multithreading Hardware computer science computer architecture Instruction sets Out of order program processors Protocols

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A tool for analysing logics

A tool for analysing logics

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作者： Veloso, Sheila R.M. Veloso, Paulo A.S. Veloso, Paula M. Systems and Computer Engin. Dept. Fac. of Engineering UERJ: State University of Rio de Janeiro Rio de Janeiro RJ Brazil Systems and Computer Engineering Program COPPE UFRJ: Federal University of Rio de Janeiro Rio de Janeiro RJ Brazil Mathematics Dept. ICEx UFMG: Federal University of Minas Gerais Belo Horizonte MG Brazil

We introduce and examine a tool for analysing logics. This algebraic tool, coming from some ideas introduced by J. Piaget, provides condensed information about a logic (with emphasis on the behavior of a unary symbol), as such, it can be employed for analysing and, to some extent, comparing logics. © 2011 Elsevier B.V. All rights reserved.

关键词： computer circuits

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