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Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for Homogeneous MPSoCs

computers, Materials & Continua 2023年第1期74卷 965-981页

作者： Hamayun Khan Irfan Ud din Arshad Ali Sami Alshmrany Department of Electrical Engineering Faculty of Engineering&Technology Superior University Lahore54000Pakistan Department of Computer Science Faculty of Computer Science&IT Superior University Lahore54000Pakistan Faculty of Computer and Information Systems Islamic University of MadinahAl Madinah Al Munawarah42351Saudi Arabia

Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor *** the advancement of technology,the performance management of central processing unit(CPU)is *** densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip *** energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life *** this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power *** selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)*** in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more *** proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple *** performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for *** are running and accurately scheduled to make an energy-efficient

关键词： Dynamic power management dynamic voltage&frequency scaling dynamic thermal management multiprocessor system on chip complementary metal oxide semiconductor reliability

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Latest Innovations in Intelligent Network-on-Chip Architectures: A Systematic Review 17

Latest Innovations in Intelligent Network-on-Chip Architectu...

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17th IEEE/ACM International Workshop on Network on Chip Architectures, NoCArc 2024

作者： Kakoulli, Elena Neapolis University Pafos Intelligent Systems Laboratory Department of Computer Science Pafos Cyprus Cyprus University of Technology Electrical Engineering and Computer Engineering and Informatics Limassol Cyprus

ISBN: (纸本)9798331506421

This review investigates the latest advancements in intelligent Network-on-Chip (NoC) architectures, focusing on innovations from 2022 to 2024. The integration of Artificial Intelligence (AI) and Machine Learning (ML) into NoC designs has driven significant improvements in performance, scalability, energy efficiency, and security. Key contributions include AI/ML-driven techniques to optimize routing, reduce latency, manage power consumption, and enhancing security against emerging threats. Despite these advancements, challenges such as computational overhead and integration complexities remain. This review consolidates these findings, addresses existing challenges, and proposes future research directions to further leverage AI and ML for developing robust and adaptable NoC architectures. © 2024 IEEE.

关键词： Federated learning

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IoT Based Smart Refrigerator Using Machine Learning 2

IoT Based Smart Refrigerator Using Machine Learning

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2nd International Conference on Artificial Intelligence and Machine Learning Applications, AIMLA 2024

作者： Devanath, B. Dharunish, A.P. Mohana Bharathi, S. Suganth, R. Banupriya, V. Ramesh, M. M Kumarasamy College of Engineering Department of Electrical and Electronics Engineering Karur India M Kumarasamy College of Engineering Department of Computer Science and Business Systems Karur India

ISBN: (数字)9798350349221

ISBN: (纸本)9798350349221

The fridge is the most constantly employed menage/ kitchen electrical device encyclopedically for conserving food. The leading sectors of smart widgets include refrigerators in the kitchen. The Web of Effects (IoT) denotes the tools and systems employed to link the factors deduced from the detectors and selectors. Primarily this contrivance is employed for different purposes such as storing flora, fruits, etc. This design transforms any pre-existing fridge into an intelligent, budget-friendly outfit with exercise sensors. The proposed design is educated and worked grounded on the medium of learning machines, and it contrasts the condition of the aliment, for case, Mass, quantum, etc. The significance of this undertaking will involve barring food decay, dwindling affections, and promoting a more restorative way of life for contemporary mortal beings. The arrangement of dish recommendations grounded on the veggies being in the caddy is carried out through an abecedarian algorithm of machine literacy, which categorizes the vegetables grounded on the tinges, latterly suggesting a specific form. It'll be canny enough to warn the stoner IoT about the present condition of food papers through an Android operation on our cellular device. © 2024 IEEE.

关键词： Refrigerators

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High-Throughput Independent Component Analysis Processor for Full Duplex systems

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IEEE Journal on Selected Areas in Communications 2023年第9期41卷 2821-2832页

作者： Cheng, Jen-Hao Chang, Tien-Min Shen, Chung-An Fouda, Mohammed E. Eltawil, Ahmed M. National Taiwan University of Science and Technology Department of Electronic and Computer Engineering Taipei10607 Taiwan University of California at Irvine Electrical Engineering and Computer Science Department IrvineCA92697 United States King Abdullah University of Science and Technology Electrical and Computer Engineering Program Thuwal23955 Saudi Arabia

This paper presents the algorithm and very-large-scale integration (VLSI) architecture of a high-throughput and highly efficient independent component analysis (ICA) processor for self-interference cancellation (SIC) in in-band full-duplex (IBFD) systems. This is the first VLSI architecture reported in the literature based on the state-of-the-art entropy bound minimization (EBM) approach. A novel ICA algorithm is presented in this paper with momentum gradient descent optimization. Simulation results show that the number of iterations for the proposed algorithm is significantly reduced compared to the conventional ICA algorithms. Furthermore, a novel early-distribution estimation scheme is proposed in the designed ICA processor to compute multiple distribution functions with low latency and low complexity. The processing flow and the efficiency for the hardware utilization are specifically designed so that the processing speed is maximized with minimum employment of hardware components. The proposed ICA processor is designed and implemented based on the application-specific-integrated circuit (ASIC) flow. The post-layout estimations show that compared with the conventional EBM-based scheme, the proposed design improves the throughput and efficiency by 30x. In addition, compared to prior designs shown in the literature, the proposed ICA processor also demonstrates a significant enhancement in terms of throughput and efficiency. © 1983-2012 IEEE.

关键词： VLSI circuits

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Real Time Chest X-Ray Interpretation Applying Vision Transformer for Tuberculosis Detection

Real Time Chest X-Ray Interpretation Applying Vision Transfo...

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2024 International Conference on computer engineering, Network and Intelligent Multimedia, CENIM 2024

作者： Irhamsyah, Muhammad Roslidar Yunidar Al Lail Qadrillah, M. Nasaruddin Arnia, Fitri Munadi, Khairul Universitas Syiah Kuala Post Graduate Program in Engineering Banda Aceh2311 Indonesia Faculty of Engineering Department of Electrical and Computer Engineering 2311 Indonesia

ISBN: (纸本)9798350368802

Tuberculosis (TB) is an infectious disease that can attack the lungs and other organs. In the diagnosis of TB, the interpretation of X-ray radiological images requires special skills from medical specialists. However, the lack of experience of medical personnel and focus on X-ray examinations can be a challenge for radiologists because it has the potential to cause diagnostic errors in image interpretation. Therefore, we proposed a web-based application of real-time chest X-ray interpreter by integrating the deep learning model of Vision Transformer (ViT) to interpret chest X-ray images. The inference model was trained and tested on 652 normal and 652 tuberculosis X-ray images. The data preprocessing of Contrast Adaptive Histogram Equalization (CLAHE) was implemented to increase chest X-ray image contrast as well as inference model performance. The proposed real time system can inteprete the tested chest x-ray images with an accuracy of 95% and with simulation duration time of 4.7 seconds. © 2024 IEEE.

关键词： Diagnosis

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The Impact of SMOTE and ADASYN on Random Forest and Advanced Gradient Boosting Techniques in Telecom Customer Churn Prediction 10

The Impact of SMOTE and ADASYN on Random Forest and Advanced...

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10th International Conference on Web Research, ICWR 2024

作者： Imani, Mehdi Ghaderpour, Zahra Joudaki, Majid Beikmohammadi, Ali Stockholm University Department of Computer and System Sciences Stockholm10691 Sweden Ayatollah Boroujerdi University Electrical and Computer Engineering Boroujerd Iran University of Kashan Electrical and Computer Engineering Kashan Iran Stockholm University Department of Computer and Systems Sciences StockholmSE-16455 Sweden

ISBN: (纸本)9798350394986

This paper explores the capability of various machine learning algorithms, including Random Forest and advanced gradient boosting techniques such as XGBoost, LightGBM, and CatBoost, to predict customer churn in the telecommunications sector. For this analysis, a dataset available to the public was employed. The performance of these algorithms was assessed using recognized metrics, including Accuracy, Precision, Recall, F1-score, and the Receiver Operating Characteristic Area Under Curve (ROC AUC). These metrics were evaluated at different phases: subsequent to data preprocessing and feature selection;following the application of SMOTE and ADASYN sampling methods;and after conducting hyperparameter tuning on the data that had been adjusted by SMOTE and *** outcomes underscore the notable efficiency of upsampling techniques such as SMOTE and ADASYN in addressing the imbalance inherent in customer churn prediction. Notably, the application of random grid search for hyperparameter optimization did not significantly alter the results, which remained comparatively unchanged. The algorithms' performance post-ADASYN application marginally surpassed that observed after SMOTE application. Remarkably, LightGBM achieved an exceptional F1-score of 89% and an ROC AUC of 95% subsequent to the ADASYN sampling technique. This underlines the effectiveness of advanced boosting algorithms and upsampling methods like SMOTE and ADASYN in navigating the complexities of imbalanced datasets and intricate feature interdependencies. © 2024 IEEE.

关键词： Machine learning

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CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks 25

CAC 2.0: A Corrupt and Correct Logic Locking Technique Resil...

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25th IEEE Latin American Test Symposium, LATS 2024

作者： Aksoy, Levent Yasin, Muhammad Pagliarini, Samuel National University Of Sciences And Technology Department Of Computer And Software Engineering Islamabad Pakistan Tallinn University Of Technology Department Of Computer Systems Tallinn Estonia Carnegie Mellon University Department Of Electrical And Computer Engineering Pittsburgh United States

ISBN: (纸本)9798350365559

Logic locking proposed to protect integrated circuits from serious hardware threats has been studied extensively over a decade. In these years, many logic locking techniques have been proven to be broken. The state-of-the-art logic locking techniques, including the prominent corrupt and correct (CAC) technique, are resilient to satisfiability (SAT)-based and removal attacks, but vulnerable to structural analysis attacks. To overcome this drawback, this paper introduces an improved version of CAC, called CAC 2.0, which increases the search space of structural analysis attacks using obfuscation. To do so, CAC 2.0 locks the original circuit twice, one after another, on different nodes with different number of protected primary inputs using CAC, while hiding original protected primary inputs among decoy primary inputs. This paper also introduces an open source logic locking tool, called HIID, equipped with well-known techniques including CAC 2.0. Our experiments show that CAC 2.0 is resilient to existing SAT-based, removal, and structural analysis attacks. To achieve this, it increases the number of key inputs at most 4× and the gate-level area between 30.2% and 0.8% on circuits with low and high complexity with respect to CAC. © 2024 IEEE.

关键词： Structural analysis

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A 4.5 μW Miniaturized 3-Channel Wireless Intra-Cardiac Acquisition System

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IEEE Transactions on Biomedical Circuits and systems 2023年第5期17卷 1097-1110页

作者： Rezaeiyan, Yasser Koolivand, Yarallah Zamani, Milad Shoaei, Omid Akbari, Meysam Moradi, Farshad Tang, Kea-Tiong Integrated Circuits and Electronics Laboratory Department of Engineering Aarhus University Aarhus8200 Denmark Electrical Engineering KN Toosi University of Technology Tehran15418-49611 Iran Bio-Integrated Systems Lab School of Electrical and Computer Engineering University of Tehran Tehran*** Iran Department of Electrical Engineering University of Kurdistan Sanandaj*** Iran Department of Electrical Engineering National TsingHua University Hsinchu30013 Taiwan

This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.1%. Furthermore, the boosting technique enhances the feedback resistance, leading to a reduction in the size of the feedback capacitor and, consequently, the overall size. To make the modulator's output frequency resilient to temperature and process changes, coarse and fine-tuning algorithms are used. The front-end channel is capable of extracting the intra-cardiac signal with an effective number of bits of 8.9, while exhibiting an input-referred noise of less than 2.7 μ Vrms, and consuming 200 nW per channel. The front-end output is encoded by an ASK-PWM modulator, which drives an on-chip transmitter at 13.56 MHz. The proposed System-on-Chip (SoC) is fabricated in a 0.18 μ m standard CMOS technology and consumes 4.5 μW while occupying 1.125 mm2. © 2023 IEEE.

关键词： Transmitters

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Orbiting Optimization Model for Tracking Voltage Security Region Boundary in Bulk Power Grids

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CSEE Journal of Power and Energy systems 2022年第2期8卷 476-487页

作者： Xue Li Tao Jiang Linquan Bai Xiao Kou Fangxing Li Houhe Chen Guoqing Li the Department of Electrical Engineering Northeast Electric Power UniversityJilin 132012China the Department of Systems Engineering and Engineering Management University of North Carolina at CharlotteCharlotteNC28223 USA the Department of Electrical Engineering and Computer Science University of TennesseeKnoxvilleTN37996 USA

A voltage security region(VSR)is a powerful tool for monitoring the voltage security in bulk power grids with high penetration of *** can prevent cascading failures in wind power integration areas caused by serious over or low voltage *** bottlenecks of a VSR for practical applications are computational efficiency and *** bridge these gaps,a general optimization model for tracking a voltage security region boundary(VSRB)in bulk power grids is developed in this paper in accordance with the topological characteristics of the ***,the initial VSRB point on the VSRB is examined with the traditional OPF by using the base case parameters as initial ***,the rest of the VSRB points on the VSRB are tracked one after another,with the proposed optimization model,by using the parameters of the tracked VSRB point as the initial value to explore its adjacent VSRB *** proposed approach can significantly improve the computational efficiency of the VSRB tracking over the existing algorithms,and case studies,in the WECC 9-bus and the Polish 2736-bus test systems,demonstrate the high accuracy and efficiency of the proposed approach on exploring the VSRB.

关键词： Optimal power flow(OPF) stress direction voltage security critical point voltage security region voltage security region boundary

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A deep decentralized privacy-preservation framework for online social networks

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Blockchain(Research and Applications) 2024年第4期5卷 163-174页

作者： Samuel Akwasi Frimpong Mu Han Emmanuel Kwame Effah Joseph Kwame Adjei Isaac Hanson Percy Brown School of Computer Science and Communication Engineering Jiangsu UniversityZhenjiang212013China Department of Computer Engineering Ghana Communication Technology UniversityAccraPMB 100Ghana Department of Electrical&Electronic Engineering Ghana Communication Technology UniversityAccraPMB 100Ghana Department of Computer Science and Information Systems Ashesi UniversityAccra3042Ghana Department of Telecommunication Engineering Ghana Communication Technology UniversityAccraPMB 100Ghana

This paper addresses the critical challenge of privacy in Online Social Networks(OSNs),where centralized designs compromise user *** propose a novel privacy-preservation framework that integrates blockchain technology with deep learning to overcome these *** methodology employs a two-tier architecture:the first tier uses an elitism-enhanced Particle Swarm Optimization and Gravitational Search Algorithm(ePSOGSA)for optimizing feature selection,while the second tier employs an enhanced Non-symmetric Deep Autoencoder(e-NDAE)for anomaly ***,a blockchain network secures users’data via smart contracts,ensuring robust data *** tested on the NSL-KDD dataset,our framework achieves 98.79%accuracy,a 10%false alarm rate,and a 98.99%detection rate,surpassing existing *** integration of blockchain and deep learning not only enhances privacy protection in OSNs but also offers a scalable model for other applications requiring robust security measures.

关键词： Preprocessing Privacy-preservation Blockchain Deep learning Online social network

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