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Annual Symposium on Simulation

作者： S. Nikoletseas I. Chatzigiannakis H. Euthimiou A. Kinalis A. Antoniou G. Mylonas Department of Computer Engineering and Informatics University of Patras Patras Greece Computer Technology Institute Patras Greece Department of Computer Department of Computer University of Patras Patras Greece

Wireless sensor networks are comprised of a vast number of ultra-small, autonomous computing and communication devices, with restricted energy, that cooperate to accomplish a large sensing task. In this work: a) we propose extended versions of two data propagation protocols for such networks: the sleep-awake probabilistic forwarding protocol (SW-PFR) and the hierarchical threshold sensitive energy efficient network protocol (H-TEEN). These non-trivial extensions improve the performance of the original protocols, by introducing sleep-awake periods in the PFR protocol to save energy, and introducing a hierarchy of clustering in the TEEN protocol to better cope with large networks; b) we implemented the two protocols and performed an extensive simulation comparison of various important measures of their performance with a focus on energy consumption; c) we investigate in detail the relative advantages and disadvantages of each protocol; and d) we discuss a possible hybrid combination of the two protocols towards optimizing certain goals.

关键词： Energy efficiency Protocols Intelligent networks Magnetic sensors Acoustic sensors computer networks Chemical and biological sensors Power engineering and energy informatics Wireless sensor networks

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Diminished-1 modulo 2/sup n/ + 1 squarer design

Diminished-1 modulo 2/sup n/ + 1 squarer design

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Euromicro Symposium on Digital System Design

作者： H.T. Vergos C. Efstathiou Computer Technology Institute Patras Greece Computer Engineering & Informatics Department University of Patras Patras Greece Informatics Department TEI Athens Athens Greece

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2/sup n/ + 1. To avoid using (n + 1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2/sup n/ + 1 arithmetic applications. In this paper, for the first time in the open literature, we formally derive modulo 2/sup n/ + 1 squarers that adopt the diminished-1 number system. The resulting implementations are built using only full- or half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.

关键词： Arithmetic Cryptography Concurrent computing Adders Circuits Digital signal processors Digital signal processing Digital filters Filtering Digital modulation

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Scan cell ordering for low power BIST

Scan cell ordering for low power BIST

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IEEE computer Society Annual Symposium on VLSI

作者： M. Bellos D. Bakalis D. Nikolos Computer Engineering & Informatics Department University of Patras Patras Greece Research Academic Computer Technology Institute Patras Greece

Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine the use of transition frequency based on scan cell ordering techniques in pseudorandom scan based BIST in order to reduce average power dissipation. We also propose the resetting of the input register of the circuit together with ordering of its elements to further reduce average power dissipation. Experimental results indicate that the proposed techniques can reduce average power dissipation up to 57.7%.

关键词： Built-in self-test Very large scale integration computer Society

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Performance evaluation of an IPv6-capable H323 application

Performance evaluation of an IPv6-capable H323 application

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International Conference on Advanced Information Networking and Applications (AINA)

作者： C. Bouras A. Gkamas D. Primpas K. Stamos Computer Engineering and Informatics Department University of Patras Patras Greece Research Academic Computer Technology Institute Patras Greece

OpenH323 is an open source H.323 implementation that has been ported to IPv6. In this paper we briefly introduce the library architecture and the performance criteria with which the ported version should be evaluated. We then present a variety of experiments that we conducted in order to comparatively evaluate the IPv4 and IPv6 protocol stacks. We also present the results of some initial experiments comparing IPv4 and IPv6 performance under congested network links and the conclusions that they lead us to.

关键词： Protocols Libraries Internet Network address translation Quality of service Programming profession Application software informatics computer architecture Shape

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An adaptive admission control algorithm for bandwidth brokers

An adaptive admission control algorithm for bandwidth broker...

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IEEE International Symposium on Network Computing and Applications

作者： Ch. Bouras K. Stamos Computer Engineering and Informatics Department University of Patras Patras Greece Research Academic Computer Technology Institute Patras Greece

This work focuses on the operation of the bandwidth broker, an entity that is responsible for managing the bandwidth within a network domain and for the communication with bandwidth brokers of neighboring domains. A very important aspect of the bandwidth broker is its admission control module that determines whether the bandwidth reservation requests are going to be accepted or not. We summarize the status of the current research in this field and propose architecture for the admission control module that aims at achieving a satisfactory balance between maximizing the resource utilization for the network provider and minimizing the overhead of the module. This is achieved by gathering and examining sets of book-ahead requests and by adapting the size of the set to be examined so that the network utilization and the computation overhead are appropriately balanced.

关键词： Programmable control Adaptive control Admission control Bandwidth Resource management computer networks Diffserv networks computer architecture informatics Electronic mail

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Towards Realistic Modeling of Time-Table Information through the Time-Dependent Approach

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Electronic Notes in Theoretical computer Science 2004年 92卷 85-103页

作者： Evangelia Pyrga Frank Schulz Dorothea Wagner Christos Zaroliagis Computer Technology Institute P.O. Box 1122 26110 Patras Greece and Department of Computer Engineering and Informatics University of Patras 26500 Patras Greece Department of Computer Science University of Karlsruhe 76128 Karlsruhe Germany

We consider optimal itinerary problems in time-table information systems supporting a vast number of on-line queries. We exhibit two important extensions of the time-dependent approach to model realistic versions of the Earliest Arrival and Minimum Number of Transfer problems, as well as of a combination of them, that could not be modeled by the original version of the time-dependent approach. We also provide heuristics that speed up implementations and present preliminary experimental results with real-world data.

关键词： Time-table information time-dependent model shortest path earliest arrival minimum number of transfers

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Accumulator based test-per-scan BIST

Accumulator based test-per-scan BIST

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IEEE Symposium on On-Line Testing (IOLTS)

作者： P. Karpodinis D. Kagaris D. Nikolos Computer Engineering and Informatics Department University of Patras Patras Greece Computer Technology Institute Patras Greece Electrical & Computer Engineering Department Southem Illinois University Carbondale IL USA

Arithmetic function modules, which are available in many circuits, can be utilized to generate test patterns and compact test responses. Recently, an accumulator behaving in test mode as a non-linear feedback shift register (NLFSR) has been proposed for bit-serial test pattern generation. However, this structure has the disadvantage that the maximum period of the generated bit sequence depends on the suitable selection of a constant additive value (CAV), which is based on an exhaustive trial and error procedure. In this paper, we propose a slightly modified structure and a heuristic for speeding up significantly the searching of a suitable CAV. We also show, experimentally, that the proposed structure, in most cases, compares favorably to LFSRs and the other arithmetic function based bit-serial sequence generators.

关键词： Built-in self-test Test pattern generators Circuit testing Hardware Feedback Shift registers Arithmetic Compaction Degradation informatics

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Low power testing by test vector ordering with vector repetition

Low power testing by test vector ordering with vector repeti...

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IEEE International Symposium on Quality Electronic Design

作者： M. Bellos D. Bakalis D. Nikolos X. Kavousianos Computer Engineering & Informatics Department University of Patras Patras Greece Research Academic Computer Technology Institute Patras Greece Computer Science Department University of Ioannina (UoI) Ioannina Greece

Test vector ordering with vector repetition has been presented as a method to reduce the average as well as the peak power dissipation of a circuit during testing. Based on this method, in this paper we present some techniques that can be used to further reduce the average power dissipation. Experimental results validate that the proposed techniques achieve considerable savings in energy and average power dissipation while reducing the length of the resulting test sequences compared to the original method.

关键词： Circuit testing Power dissipation Switching circuits Energy dissipation TV Scholarships Delay System testing Power system reliability Power engineering and energy

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An efficient test vector ordering method for low power testing

An efficient test vector ordering method for low power testi...

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IEEE computer Society Annual Symposium on VLSI

作者： X. Kavousianos D. Bakalis M. Bellos D. Nikolos Computer Science Department University of Ioannina (UoI) Ioannina Greece Computer Engineering & Informatics Department University of Patras Patras Greece Research Academic Computer Technology Institute Patras Greece

This paper presents a novel test vector ordering method for average power consumption minimization. The proposed method orders the test vectors taking into account the expected switching activity at the primary inputs and at a very small set of internal lines of the circuit under test. The computational time required by the proposed method is very small while the power reduction achieved is very close to the best, with respect to power reduction, most time-consuming method. Experimental results show that apart from average power reduction, the proposed method achieves significant peak power reduction too.

关键词： System testing Very large scale integration computer Society

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Dynamic Shortest Paths Containers

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Electronic Notes in Theoretical computer Science 2004年 92卷 65-84页

作者： Dorothea Wagner Thomas Willhalm Christos Zaroliagis Institut für Logik Komplexität und Deduktionssysteme Universität Karlsruhe 76128 Karlsruhe Germany Computer Technology Institute and Department of Computer Engineering & Informatics University of Patras 26500 Patras Greece

Using a set of geometric containers to speed up shortest path queries in a weighted graph has been proven a useful tool for dealing with large sparse graphs. Given a layout of a graph G =( V , E ), we store, for each edge ( u , v )∈ E , the bounding box of all nodes t ∈ V for which a shortest u - t -path starts with ( u , v ). Shortest path queries can then be answered by Dijkstraś restricted to edges where the corresponding bounding box contains the target. In this paper, we present new algorithms as well as an empirical study for the dynamic case of this problem, where edge weights are subject to change and the bounding boxes have to be updated. We evaluate the quality and the time for different update strategies that guarantee correct shortest paths in an interesting application to railway information systems, using real-world data from six European countries.

关键词： geometric container dynamic shortest path graph layout

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