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On interval routing schemes and treewidth 21st

On interval routing schemes and treewidth

引用

21st International Workshop on Graph-Theoretic Concepts in computer Science, WG 1995

作者： Bodlaender, Hans L. Tan, Richard B. Thilikos, Dimitris M. Van Leeuwen, Jan Department of Computer Science Utrecht University P.O. Box 80.089 Utrecht3508 TB Netherlands Department of Computer Science University of Sciences and Arts of Oklahoma Chickasha Oklahoma73018 United States Computer Technology Institute P.O. Box 1122 Patras26110 Greece Department of Computer Engineering and Informatics University of Patras Rio Patras26500 Greece

ISBN: (纸本)3540606181

In this paper, we investigate which processor networks allow k-label Interval Routing Schemes, under the assumption that costs of edges may vary. We show that for each fixed k ≥ 1, the class of graphs allowing such routing schemes is closed under minor-taking in the domain of connected graphs, and hence has a linear time recognition algorithm. This result connects the theory of compact routing with the theory of graph minors and treewidth. We also show that every graph that does not contain K2,r as a minor has treewidth at most 2r – 2. In case the graph is planar, this bound can be lowered to r + 2. As a consequence, graphs that allow k-label Interval Routing Schemes under dynamic cost edges have treewidth at most 4k, and treewidth at most 2k + 3 if they are planar. Similar results are shown for other types of Interval Routing Schemes. © 1995, Springer-Verlag Berlin Heidelberg 1995.

关键词： Routing protocols

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Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs)

Optimal synthesis of differential cascode voltage switch (DC...

引用

European Design Automation Conference

作者： T. Karoubalis G.Ph. Alexiou N. Kanopoulos Computer Technology Institute Patras Greece Department of Computer Engineering and Informatics University of Patras Patras Greece Center for Digital System Engineering RTI International Inc. NC USA

This paper presents a method for near-optimum synthesis of Differential Cascade Voltage Switch (DCVS) logic circuits using Ordered Binary Decision Diagrams (OBDD). The method presented produces efficient DCVS circuit structures in terms of transistor count which positively affects the circuit area and performance. The proposed method is also very practical because it produces results with short run-times on a design workstation. The paper presents experimental results that demonstrate the use and the efficiency of the proposed DCVS synthesis method. This method is the basis for a CAD tool that allows automatic synthesis of fault secure circuits based on the DCVS technology.

关键词： Switches Voltage Circuit synthesis Switching circuits Logic circuits Data structures Boolean functions Runtime Workstations Design automation

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On the testability of purely recursive digital filters 6th

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6th International Conference on Parallel Architectures and Languages Europe, PARLE 1994

作者： Vergis, Anastasios Verykios, Vassilios Department of Computer Engineering and Informatics University of Patras Patras26500 Greece Computer Technology Institute of Greece Greece

ISBN: (纸本)9783540581840

This paper presents a method for generating tests for purely recursive digital filters. Generally, these consist of modules such as adders, multipliers and memory elements that are interconnected to realize complex functions. Our approach uses regular propagating test sequences that deal with the inherent parallel form of these structures. We derive a test sequence for the application of test vectors from a predetermined single-cell test set to all the cells of an Nth order filter. Reduced testing time is achieved by using pipelining in vector application. A full speed test sequence is considered with a minimal number of test vectors. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Bandpass filters

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Adaptive nonlinear algorithms for radar tracking with roll angle measurements of maneuvering targets

Adaptive nonlinear algorithms for radar tracking with roll a...

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Mediterranean Electrotechnical Conference (MELECON)

作者： D.G. Lainiotis I.A. Marinitsis S.K. Katsikas Department of Electrical & Computer Engineering Florida Institute of Technology Melbourne FL USA Department of Computer Engineering and Informatics University of Patras Patras Greece Department of Mathematics University of Aegean Karlovassi Greece

The problem of radar tracking a civilian maneuvering aircraft utilizing on board available measurements of the aircraft roll angle is addressed. Two algorithms belonging to the family of adaptive multimodel partitioning algorithms are designed for this problem and evaluated via simulation experiments with regards to their performance. It is found that these algorithms perform very well in tracking a maneuvering aircraft, and, naturally, far better than previously reported non-adaptive algorithms.< >

关键词： Radar tracking Goniometers Acceleration Aircraft Equations Accelerometers Noise measurement Sampling methods Filters Trajectory

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Fast parallel constraint satisfaction 20th

引用

20th International Colloquium on Automata, Languages and Programming, ICALP 1993

作者： Kirousis, Lefteris M. Department of Computer Engineering and Informatics University of Patras Rio Patras265 00 Greece Computer Technology Institute P.O. Box 1122 Patras261 10 Greece

ISBN: (纸本)9783540569398

A Constraint Satisfaction Problem (CSP) involves searching for an assignment of values to a given set of variables so that the values assigned satisfy a given set of constraints. The general CSP is NP-complete. To confront the intractability of the general CSP, relaxation procedures have been devised: instead of searching for a globally consistent assignment of values to the variables, try to restrict the domain of values of each variable in a way that ensures local consistency only. The relaxation procedures are efficient, but have been proved to be inherently sequential. In this paper, we define a class of CSPs for which a global solution can be found by a fast parallel algorithm. No relaxation preprocessing is needed for the parallel algorithm to work. The result is motivated from the problem of labelling a 2-D line drawing of a 3-D object by the Clowes-Huffman-Malik labelling scheme--an important application of CSP in computer vision. For such a labelling CSP, the constraint graph can be general, but the constraint relations are usually of the type we call implicational. It is shown here that a CSP with this type of constraint relations (and no restrictions on its graph) can be solved by an efficient (i.e., with polynomial time complexity) sequential algorithm. Also, it is shown that it can be solved by a fast parallel algorithm that executes in time O(log3n) with O((m + n3)/logn) processors on a Exlusive-Read-Exclusive-Write Parallel Random Access Machine (n is the number of variables and m is the number of constrain relations-the constraint relations may have arity more than two). © Springer-Verlag Berlin Heidelberg 1993.

关键词： Constraint satisfaction problems

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New LS and SVD based methods for estimating frequencies of complex sinusoids

New LS and SVD based methods for estimating frequencies of c...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： G.V. Moustakides K. Berberidis Department of Computer Engineering University of Patras Patras Greece Computer Technology Institute CTI Patras Greece

New least squares (LS) and singular value decomposition (SVD) based methods for the estimation of frequencies of complex sinusoids in white noise are presented. The methods are based on a new prediction problem that has some very useful properties leading to algorithms that have considerably reduced complexity. This is achieved without the sacrifice of any significant measure of performance with respect to existing methods that are based on the forward-backward predictor.< >

关键词： Frequency estimation Polynomials White noise Symmetric matrices Signal to noise ratio Spectral analysis Noise reduction Prediction methods Filters

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The perfect and imperfect clocks approach to performance analysis of basic timestamp ordering in distributed databases

The perfect and imperfect clocks approach to performance ana...

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International Conference on Computing and Information (ICCI)

作者： C.J. Bouras P.G. Spirakis Department of Computer Science and Engineering University of Patras Greece Computer Technology Institute CTI Greece Patras Greece

Locking and timestamping are two popular approaches to concurrency control in database systems. Although more than a dozen analytic performance studies of locking techniques have recently appeared in the literature, analytic performance study of timestamp-based concurrency algorithms largely remains an unexplored area. This paper presents a model of a distributed database system which provides a framework to study the performance of timestamp ordering concurrency control. We exhibit an analytical solution, which has been tested with extensive simulation. The accuracy seems to be very high. We assume perfect and also imperfect clocks for synchronization and quantify the way in which local clock inaccuracies affect the phenomenon of transaction conflicts. In particular, we derive a lot of interesting performance measures such as probability of abort, throughput and others.< >

关键词： Clocks Performance analysis Concurrency control Database systems Algorithm design and analysis Concurrent computing Testing Analytical models Synchronization Particle measurements

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Efficient algorithms for checking the atomicity of a run of read and write operations 7th

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7th International Workshop on Distributed Algorithms, WDAG 1993

作者： Kirousis, Lefteris M. Veneris, Andreas G. Department of Computer Engineering and Informatics University of Patras Rion265 00 Greece Computer Technology Institute P.O. Box 1122 Patras261 10 Greece Department of Computer Science University of Illinois at Urbana-Champaign Room 2412 DCL 1304 West Springfield Avenue UrbanaIL61801 United States

ISBN: (纸本)9783540572718

Let X1,…, Xc be variables shared by a number of processors p1,…, Pq which operate in a totally asynchronous and wait-free manner. An operation by a processor is either a write to one of the variables or a read of the values of all variables. Operations are not assumed to be instantaneous and may arbitrarily overlap in time. A succession of possibly overlapping operations a1,…, an (i.e., a run) is said to be atomic, if these operations can be serialized in a way compatible with any existing precedences among them and so that any read operation returns for each variable the value of the most recent —with respect to the serialization— write operation on this variable. This paper examines the complexity of the combinatorial problem of testing a run for atomicity. First it is pointed out that when there is only one shared variable or when only one processor is allowed to write to each variable, known theorems lead to polynomial-time algorithms for checking the atomicity of a run (the variable of the time-complexity function is the number of operations in the run). It is then proved that checking atomicity has polynomial-time complexity in the general case of more than one variables and with all procesors allowed to read and write. For the proof, the atomicity problem is reduced to the problem of consecutive 1s in matrices. The reduction entails showing a combinatorial result which might be interesting on its own. © Springer-Verlag Berlin Heidelberg 1993.

关键词： Polynomial approximation

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Timing verification of NMOS logic circuits

Timing verification of NMOS logic circuits

引用

IEEE Pacific Rim Conference on Communications, computers and Signal Processing

作者： E. Macii J. Wilson Department of Electrical and Computer Engineering University of Colorado Boulder CO USA Dip. di Äutornatica e Informatics Politecnico di Torino Torino Italy Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

A set of procedures that can be used to check NMOS logic circuits for timing errors is presented. The procedures find the path which could cause timing errors, and calculate the delays along those paths. The determination of these delays can be performed either before layout, using estimated values for the interconnected capacitance, or after layout, when the exact values are available. The advantage of using path delay computation for timing verification, as opposed to detailed timing simulation, is also discussed.< >

关键词： Timing MOS devices Logic circuits Clocks Propagation delay Delay estimation Capacitance Delay effects computer errors Computational modeling

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Active vision with two differentiated visual fields 11

Active vision with two differentiated visual fields

引用

11th IAPR International Conference on Pattern Recognition, IAPR 1992

作者： Sato, Yukio Toyoda, Masanobu Department of Electrical and Computer Engineering Nagoya Institute of Technology Nagoya466 Japan Science and Technology Computation Division CTI: Computer Technology Integrator Co. Ltd. Nagoya455 Japan

ISBN: (纸本)081862910X

A vision system is proposed that has two differentiated visual fields, i.e., peripheral and central, and the fixation point to the scene is actuated actively. The proposed vision system is aiming at an active vision system that recognizes environment actively by gazing at each object of interest. To build this system, we developed a vision system with two CCD cameras of which fixation points are controlled by a computer. A fundamental vision model is proposed that consists of five independent neural network modules. Each module is educated individually and processes visual information independently. To signify the feasibility of the proposed vision model, some fundamental experiments were carried out. © 1992 IEEE.

关键词： CCD cameras

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