In this paper, we propose a novel algorithm based on evolutionary computation techniques to extract an optimal user profile. This method originates from the simulation of the human immune system for finding binary str...
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This paper proposes a clustering method for nominal and numerical data based on Rough Sets and its application to knowledge discovery in the medical database. Classification is performed according to the indiscernibil...
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The continued growth of microprocessors' performance and the need for better CPU utilization, has led to the introduction of the software peripherals' approach: By this term we refer to software modules that c...
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ISBN:
(纸本)1581133642
The continued growth of microprocessors' performance and the need for better CPU utilization, has led to the introduction of the software peripherals' approach: By this term we refer to software modules that can successfully emulate peripherals that, until now, were traditionally implemented in hardware. Software implementations offer great flexibility in product design and in functional upgrades, while they have high contribution in the cost/performance ratio optimization. We focus on embedded applications, where the cost and the short time to market are the leading issues. In this paper, we study the hardware and software requirements for developing a generic microprocessor with support for software peripherals. Additionally, we present three software peripherals, a Universal Asynchronous Receiver Transmitter, a keypad controller and a dot matrix LCD controller, and we analyze their impact in CPU occupation. Finally, we explore the impact of using a software UART on system power dissipation.
The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for built-in self-test, the extra area required for e...
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ISBN:
(纸本)0769510256
The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for built-in self-test, the extra area required for embedding testing structures can be cut down efficiently. Several schemes based on accumulators, subtracters, multipliers and shift, resisters have been proposed and analyzed in the past for parallel test response compaction, whereas some efforts have also been devoted in the bit-serial response compaction case. In this paper, we analyse and evaluate the bit-serial version of a recently proposed scheme for parallel test response compaction. Experimental results on the ISCAS'85 benchmark circuits indicate that the post-compaction fault coverage drop attained by the new scheme is significantly lower than other already known accumulator-based compaction schemes.
Presents a WWW-based tool for the generation of arithmetic soft cores for a wide variety of functions, operand sizes and architectures. The tool produces structural and synthesizable VHDL and/or Verilog descriptions a...
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ISBN:
(纸本)0769512062
Presents a WWW-based tool for the generation of arithmetic soft cores for a wide variety of functions, operand sizes and architectures. The tool produces structural and synthesizable VHDL and/or Verilog descriptions and covers several arithmetic operations, such as addition, subtraction, multiplication, division, squaring, square rooting and shifting. Therefore, designs requiring arithmetic cores, as for example those in digital signal processing and multimedia applications, can be completed faster and with less effort.
Presents a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jum...
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ISBN:
(纸本)0769512909
Presents a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and minimization of the cardinality of the test set and the hardware required for the implementation of the test pattern generator. The application of the proposed technique to ISCAS '85 and the combinational part of ISCAS '89 benchmark circuits shows its superiority against the already known reseeding techniques with respect to the length of the test sequence and, in the majority of cases, the hardware required for their implementation.
A new hybrid evolutionary method is proposed. This method alleviates the dependency of pure evolutionary algorithms on the complexity of a given time series and turns out to be very reliable in identifying the correct...
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ISBN:
(纸本)9539676940
A new hybrid evolutionary method is proposed. This method alleviates the dependency of pure evolutionary algorithms on the complexity of a given time series and turns out to be very reliable in identifying the correct order and estimation the true parameters' values of a given system model. It combines the effectiveness of the multi-model partitioning theory with the robustness of evolutionary algorithms. Although the system structure is a bit complicated, simulation results show that the proposed method gives better results compared to the conventional multi-model adaptive filter algorithm and the pure evolutionary ones, since it has not only the ability to perform well in searching the whole parameter space, but also to cope with the complexity of the model and reliably lead to the correct order and the true parameters' values. The method can be implemented in a parallel environment thus increasing the computational speed.
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