Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducin...
详细信息
ISBN:
(纸本)076950325X
Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable test pattern generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9% while the introduced BIST scheme implementation overhead is very small.
In this paper, we present a method for improving the performance of classical symbolic rules. This is achieved by introducing a type of hybrid rules, called neurules, which integrate neurocomputing into the symbolic f...
详细信息
In this paper, we present a method for improving the performance of classical symbolic rules. This is achieved by introducing a type of hybrid rules, called neurules, which integrate neurocomputing into the symbolic framework of production rules. Neurules are produced by converting existing symbolic rules. Each neurule is considered as an adaline unit, where weights are considered as significance factors. Each significance factor represents the significance of the associated condition in drawing the conclusion. A rule is fired when the corresponding adaline output becomes active. This significantly reduces the size of the rule base and, due to a number of heuristics used in the inference process, increases inference efficiency.
Web based systems have been shown to be useful tools for supporting educational communication for teachers and students. In this paper we present such a system, which is an integrated distributed learning environment ...
详细信息
Web based systems have been shown to be useful tools for supporting educational communication for teachers and students. In this paper we present such a system, which is an integrated distributed learning environment (IDLE). We present the technical description of this IDLE and we discuss its main characteristics like the transmission of multimedia data over the network, the manipulation of the educational procedure and the management of the users. In addition we list the functionalities of the IDLE and also discuss some implementation issues.
In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected...
详细信息
ISBN:
(纸本)0769501044
In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected paths to be robustly testable by 20*log/sub 2/n+2 test-vector pairs, where n is the length of the shifter. The propagation delay along all other paths is a function of the delays along the selected paths.
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the integrated circuit (IC) can be used for path de...
详细信息
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the integrated circuit (IC) can be used for path delay fault testing of the IC. We show that the testing of the IC for path delay faults can be reduced to the testing of each block. Intellectual property (IP) blocks are treated as black boxes. The number of circuit paths that must be tested is almost equal to the sum of the paths that must be tested for each block.
In this paper we present an efficient implementation of a serial/parallel two's complement multiplication scheme. The proposed implementation, provided in register transfer level VHDL code, can be synthesized to a...
详细信息
In this paper we present an efficient implementation of a serial/parallel two's complement multiplication scheme. The proposed implementation, provided in register transfer level VHDL code, can be synthesized to a variety of FPGA and ASIC technologies. Experimental results based on industry tools verify the efficiency of the multiplier in terms of speed and area. The proposed implementation can be used as a building block for intellectual property (IP) based development and rapid prototyping of VLSI digital signal processing systems.
This article presents the core design of a high-speed [8 Gbps] nonblocking multicast ATM cell switch. The switch uses a self-routing ring of shift-registers to transfer cells from one port to another in a pipelined fa...
详细信息
This article presents the core design of a high-speed [8 Gbps] nonblocking multicast ATM cell switch. The switch uses a self-routing ring of shift-registers to transfer cells from one port to another in a pipelined fashion resolving output contention and efficiently handling multicast cells. The "ring" architecture is advantageous from a VLSI standpoint. A novel feature of this design is an intelligent scheduler at the output buffers which provided a physical switch level support for QoS handling. This algorithm called helix-virtual-Q emulates a "Weighted-Round-Robin Scheduling" on a single-FIFO based output buffer. An object oriented high level simulation model provided key design parameters for the synthesizeable VHDL descriptions that followed.
暂无评论