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10th IEEE Singapore International Conference on Communications Systems, ICCS 2006

作者： Ngo, Hau T. Asari, Vijayan K. Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA 23529 United States

ISBN: (纸本)1424404118

Design of a low power Multiply-and-Accumulator (MAC) unit for video processing systems exploiting the similarity of neighboring pixels in video streams is presented in this paper. The proposed technique minimizes dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, one, repeated values or repeated bit combinations are detected and control signals are generated to bypass the data and to reuse the results in the MAC unit. It is observed that the proposed scheme helps to reduce operations and switching activities in the MAC unit up to 30% which results in lower power consumption with minimal hardware overhead. © 2006 IEEE.

关键词： Pixels

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Gabor wavelet based modular PCA approach for expression and illumination invariant face recognition

Gabor wavelet based modular PCA approach for expression and ...

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35th Applied Imagery and Pattern Recognition Workshop, AIPR 2006

作者： Gudur, Neeharika Asari, Vijayan Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA 23529-0246 United States

ISBN: (纸本)0769527396

A Gabor wavelet based Modular PCA approach for face recognition is proposed in this paper. The proposed technique improves the efficiency of face recognition, under varying illumination and expression conditions for face images when compared to traditional PCA techniques. In this algorithm the face images are divided into smaller sub-images called modules and a series of Gabor wavelets at different scales and orientations are applied on these localized modules for feature extraction. A modified PCA approach is then applied for dimensionality reduction. Due to the extraction of localized features using Gabor wavelets, the proposed algorithm is expected to give improved recognition rate when compared to other traditional techniques. The performance of the proposed technique is evaluated under conditions of varying illumination, expression and variation in pose up to a certain range using standard face databases. © 2006 IEEE.

关键词： Face recognition

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Low Power Arithmetic Units for Video Processing Systems

Low Power Arithmetic Units for Video Processing Systems

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International Conference on Communication Systems

作者： Hau T. Ngo Vijayan K. Asari Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

Design of a low power multiply-and-accumulator (MAC) unit for video processing systems exploiting the similarity of neighboring pixels in video streams is presented in this paper. The proposed technique minimizes dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, one, repeated values or repeated bit combinations are detected and control signals are generated to bypass the data and to reuse the results in the MAC unit. It is observed that the proposed scheme helps to reduce operations and switching activities in the MAC unit up to 30% which results in lower power consumption with minimal hardware overhead

关键词： Arithmetic Energy consumption Frequency Clocks Capacitance Streaming media Dynamic voltage scaling Adders Hardware Circuits

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Design of a Digital Architecture for Real-Time Video, Enhancement Based on Illuminance-Reflectance Model

Design of a Digital Architecture for Real-Time Video, Enhanc...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Hau T. Ngo Ming Z. Zhang Li Tao Vijayan K. Asari Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

A design of a high performance digital architecture for a nonlinear image enhancement technique is presented in this paper. The image enhancement is based on illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions [1]. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Estimation and folding techniques are used in the hardware algorithmic design to achieve faster, simpler and more efficient architecture. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 66 Mega-pixels (Mpixels) per second.

关键词： Signal processing algorithms Image enhancement Field programmable gate arrays Digital signal processing computer architecture Image coding Streaming media Parallel processing Reflectivity Algorithm design and analysis

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Design of a High Performance Digital Architecture for Real-Time Correction of Radial Lens Distortion

Design of a High Performance Digital Architecture for Real-T...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Hau T. Ngo Vijayan K. Asari Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

The radial lens distortion correction technique based on least squares estimation corrects a distorted image by expanding it nonlinearly so that straight lines in the object space remain straight in the image space. An absolute pipelined architecture is designed to correct radial lens distortion in images by partitioning the distortion correction algorithm into four main modules. The architecture includes a COKDIC based rectangular to polar coordinate transformation module, a back mapping module for nonlinear transformation of corrected image space to distorted image space, a COKDIC based polar to rectangular coordinate transformation module, and a linear interpolation module to calculate the intensities of four pixels simultaneously in the corrected image space. The system parameters include the expanded/corrected image size, distorted image size, the back mapping coefficients, distortion center and the center of the corrected image. The hardware architecture can sustain a high throughput rate of 30 4-MegaPixel (Mpixels) frames per second (total of 120 Mpixels). The pipelined architecture design will facilitate the use of dedicated hardware that can be mounted along with the camera unit.

关键词： Optical design Lenses Nonlinear distortion Hardware Least squares approximation Algorithm design and analysis Partitioning algorithms Simultaneous localization and mapping Interpolation Pixel

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A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels

A Fully Pipelined Multiplierless Architecture for 2D Convolu...

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IEEE Asia-Pacific Conference on Circuits and Systems

作者： Ming Z. Zhang Vijayan K. Asari Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

Design of a fully pipelined multiplierless digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial results of the convolution sum. The new architecture performs computations in log-domain by utilizing low complexity log2 and inverse-log2 approximation modules. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of the multipliers in the architecture. The proposed architecture is capable of performing convolution operations for 181.3 1024 times 1024 frames or 190.1 million outputs per second with 22 times 22 kernels in a Xilinx's Virtex XC2V2000-4ff896 FPGA at maximum clock frequency of 190.1 MHz. The throughput of the new design is 3.17 times higher when compared with that of the previous implementations (Zhang et al., 2005). Evaluation in Xilinx's core generator showed that the proposed design results in 60% reduction in hardware resource when compared to the design using pipelined multipliers

关键词： Convolution Kernel computer architecture Pixel Data handling Field programmable gate arrays Clocks Frequency Throughput Hardware

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Gabor Wavelet Based Modular PCA Approach for Expression and Illumination Invariant Face Recognition

Gabor Wavelet Based Modular PCA Approach for Expression and ...

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Applied Imagery Pattern Recognition Workshop (AIPR)

作者： Neeharika Gudur Vijayan Asari Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

A Gabor wavelet based modular PCA approach for face recognition is proposed in this paper. The proposed technique improves the efficiency of face recognition, under varying illumination and expression conditions for face images when compared to traditional PCA techniques. In this algorithm the face images are divided into smaller sub-images called modules and a series of Gabor wavelets at different scales and orientations are applied on these localized modules for feature extraction. A modified PCA approach is then applied for dimensionality reduction. Due to the extraction of localized features using Gabor wavelets, the proposed algorithm is expected to give improved recognition rate when compared to other traditional techniques. The performance of the proposed technique is evaluated under conditions of varying illumination, expression and variation in pose up to a certain range using standard face databases.

关键词： Principal component analysis Lighting Face recognition Image recognition Feature extraction Vectors Statistical analysis Image databases Linear discriminant analysis Application software

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An Adaptive and Non Linear Technique for Enhancement of Extremely High Contrast Images

An Adaptive and Non Linear Technique for Enhancement of Extr...

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Applied Imagery Pattern Recognition Workshop (AIPR)

作者： Saibabu Arigela K. Vijayan Asari Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

In night time surveillance, there is a possibility of having extremely bright and dark regions in some image frames of a video sequence. A novel non linear image enhancement algorithm for digital images captured under such extremely non-uniform lighting conditions is proposed in this paper. The new technique constitutes three processes viz. adaptive intensity enhancement, contrast enhancement and color restoration. Adaptive intensity enhancement uses a specifically designed nonlinear transfer function which is capable of reducing the intensity of bright regions and at the same time enhancing the intensity of dark regions. Contrast enhancement tunes the intensity of each pixels magnitude based on its surrounding pixels. Finally, a linear color restoration process based on the chromatic information of the input image frame is applied to convert the enhanced intensity image back to a color image.

关键词： Layout Dynamic range Image coding Color Image restoration Image enhancement Displays Histograms Computational intelligence machine vision

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A hardware-efficient high performance digital architecture for run-time computation of normalized cross correlation

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WSEAS Transactions on Circuits and Systems 2006年第9期5卷 1416-1423页

作者： Zhang, Ming Z. Asari, Vijayan K. Computational Intelligence and Machine Vision Laboratory Department of Electrical and Computer Engineering Old Dominion University 231 Kaufman Hall Norfolk VA 23529 United States

A novel architecture for performing high speed computation of normalized cross correlation (NCC) is proposed in this paper. The approach promotes the concept of digital filter design to simplify window related operations and log-domain computations to eliminate all multiplications, divisions, squares, and square-roots utilizing the approximation techniques for efficient estimation of log2 and inverse-log2. The new design is capable of performing run-time calculation of NCC and the energy normalization on the fly, eliminating the frame buffering and frame sized integral tables. A new concept of uniform filter design is also presented to reduce the number of processing element arrays (PEAs) from V PEAs to 2 PEAs for a U × V window. This concept is applied to simplify the calculation of average value and energy in NCC equation. It is observed that the performance of the system with parallel pipelined architecture is able to achieve 178.5 million outputs per second (MOPS), or equivalently 142.8 billion multiplications per second, on Xilinx's Virtex II XC2V6000-4ff1152 FPGA with maximum clock frequency of 178.5MHz with 20 × 20 feature template of 8-bit resolution. Given a 1024 × 1024 data frame, the system can process over 170 frames per second (fps). Similarly, the improved full precision logarithmic module is able to sustain 212.2 MOPS at 212.2MHz maximum clock frequency with 32-bit resolution.

关键词： Digital filters

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Design of an efficient multiplier-less architecture for multi-dimensional convolution

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10th Asia-Pacific Conference on Advances in computer Systems Architecture, ACSAC 2005

作者： Zhang, Ming Z. Ngo, Hau T. Asari, Vijayan K. Computer Vision and Machine Intelligence Laboratory Department of Electrical and Computer Engineering Old Dominion University Norfolk VA 23529 United States

ISBN: (纸本)3540296433

Design of a hardware efficient multiplier-less architecture for the computation of multi-dimensional convolution is presented in this paper. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less log2 and inverse-loga modules. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The proposed approach reduces hardware resources significantly compared to other approaches while it still maintains a high degree of accuracy. The architecture is developed as a combined systolic-pipelined design that produces an output in every clock cycle after the initial latency of the system. The architecture is capable of operating with a high speed clock frequency of 99 MHz based on Xilinx's Virtex II 2v2000ff896-4 FPGA and the throughput of the system is observed as 99 MOPS (million outputs per second). © Springer-Verlag Berlin Heidelberg 2005.

关键词： computer architecture

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