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EARNPIPE : A Testbed for Smart Water Pipeline Monitoring Using Wireless Sensor Network

Procedia computer Science 2016年 96卷 285-294页

作者： Fatma Karray Alberto Garcia-Ortiz Mohamed W. Jmal Abdulfattah M. Obeid Mohamed Abid Computer and Embedded System laboratory National Engineering School of Sfax University of Sfax Sfax Tunisia Digital Research Center of Sfax Technopole of Sfax Sfax Tunisia Institute of Electrodynamics and Microelectronics (ITEM.ids) University of Bremen Bremen Germany National Center for Electronics and Photonics Technology King Abdulaziz City for Science and Technology (KACST) Riyadh Saudi Arabia

Large quantities of water are wasted daily due to leakages in pipelines. In order to decrease this waste and preserve water, advanced systems could be used. In this context, a Wireless Sensor Network (WSN) is increasingly required to optimize the reliability of the inspection and improve the accuracy of the water pipeline monitoring. A WSN solution is proposed in this paper with a view to detecting and locating leaks for long distance pipelines. It combines powerful leak detection and localization algorithms and an efficient wireless sensor node system on Chip (SoC) architecture. In fact, a novel hybrid Water Pipeline Monitoring (WPM) method has been proposed using Leak detection Predictive Kalman Filter (LPKF) and Modified Time Difference of Arrival (TDOA) method based on pressure measurements. The data collected from sensors are filtered, analyzed and compressed with the same Kalman Filter (KF) based algorithm instead of using various algorithms that deeply damage the battery of the node. The local low power pre-processing is efficient to save the power of the sensor nodes. Moreover, a laboratory testbed has been constructed using plumbing components and validated by an ARM-based prototyping platform with pressure sensors.

关键词： Water Pipeline Monitoring Wireless Sensor Network Kalman Filter system on Chip

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Efforts for Advanced Self-diagnostic Technology of Industrial computer

Efforts for Advanced Self-diagnostic Technology of Industria...

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The Society of Instrument and Control Engineers Annual Conference 2015

作者： Tadamichi Nakamura Yoichi Takayanagi Akihiro Mimura Development & Designing Industrial Computer Group Microelectronics & System Components Dept.Fuchu Operations TOSHIBA CORPORATION

According to the importance of the role of the computer used in the social infrastructure and industrial application increases, high reliability tailored for industrial applications, robustness and longterm stable operation of the needs of the computer has increased. To meet the needs, we have developed Industrial computer. But the computer still has a possible of occurring unexpected failure. Therefore, it has become necessary to make efforts toward a diagnostic technology of a cooling performance leading to a failure prediction. We describe the efforts for self-diagnostic technologies of Industrial computer.

关键词： Industrial computer,Self-diagnostic,failure prediction

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Notice of Removal: Efforts for advanced self-diagnostic technology of industrial computer

Notice of Removal: Efforts for advanced self-diagnostic tech...

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SICE Annual Conference

作者： Tadamichi Nakamura Yoichi Takayanagi Akihiro Mimura Development & Designing Industrial Computer Group Tokyo Japan Microelectronics & System Components Dept. Fuchu Operations TOSHIBA CORPORATION Tokyo Japan

According to the importance of the role of the computer used in the social infrastructure and industrial application increases, high reliability tailored for industrial applications, robustness and long-term stable operation of the needs of the computer has increased. To meet the needs, we have developed Industrial computer. But the computer still has a possible of occurring unexpected failure. Therefore, it has become necessary to make efforts toward a diagnostic technology of a cooling performance leading to a failure prediction. We describe the efforts for self-diagnostic technologies of Industrial computer.

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Low Temperature Co-fired Ceramic Package for Lab-on-CMOS Applied in Cell Viability Monitoring

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Procedia Engineering 2015年 120卷 1079-1082页

作者： Niina Halonen Joni Kilpijärvi Maciej Sobocinski Timir Datta-Chaudhuri Antti Hassinen Someshekar B. Prakash Peter Möller Pamela Abshire Elisabeth Smela Sakari Kellokumpu Anita Lloyd Spetz Microelectronics and Materials Physics Laboratories Department of Electrical Engineering P.O. Box 4500 FI-90014 University of Oulu Finland Laboratory for MicroTechnologies Department of Mechanical Engineering and the Institute for Systems Research A. James Clark School of Engineering University of Maryland College Park MD 20742 USA Integrated Biomorphic Information System Laboratory Department of Electrical & Computer Engineering and the Institute for Systems Research University of Maryland College Park MD 20742 USA Faculty of Biochemistry and Molecular Medicine University of Oulu P.O. Box 5400 FI-90014 University of Oulu Finland Advanced Design Organization Intel Corporation Hillsboro USA Division of Applied Sensor Science Department of Physics Chemistry and Biology Linköping University SE-58183 Linköping Sweden

Lab-on-CMOS chips (LOCMOS) are sophisticated miniaturized analysis tools based on integrated circuit (IC) microchips performing various laboratory functions. We have developed a low temperature co-fired ceramic (LTCC) package for a LOCMOS application regarding cytotoxicity assessment of nanomaterials. The LTCC packaged capacitance sensor chip is designed for long-term cell viability monitoring during nanoparticle exposure. The introduced LTCC package utilizes the flip chip bonding technique, and it is biocompatible as well as able to withstand the environmental conditions required to maintain mammalian cell culture directly on the surface of a complementary metal oxide semiconductor (CMOS) integrated circuit.

关键词： Lab-on-CMOS low temperature co-fired ceramics electronics packaging cytotoxicity assesment capacitance sensing

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Modeling and analysis of mobile cloud computing based on bigraph theory

Modeling and analysis of mobile cloud computing based on big...

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2nd IEEE International Conference on Mobile Cloud Computing, Services, and Engineering, MobileCloud 2014

作者： Yu, Lian Tsai, Wei Tek Wei, Xin Gao, Jerry Hildebrandt, Thomas T. Guo, Xiao Qun School of Software and Microelectronics Peking University Beijing 102600 China School of Comp. Info. and Dec. Systems Engineering Arizona State University Tempe AZ 85287 United States Dept. of Computer Engineering College of Engineering San Jose State University San Jose CA United States Process and System Models Group IT University of Copenhagen Copenhagen Denmark

ISBN: (纸本)9781479925049

A mobile cloud is a cloud infrastructure connecting to mobile devices with a variety of applications (apps). This paper proposes utilizing bigraphical reaction systems (BRSs) to model and analyze a mobile cloud including its contexts such as mobile location, power consumption, network bandwidth, and latency. Simulations and evaluations are performed by matching the reaction rules of BRS with its current agent, on different usage scenarios of mobile cloud, to demonstrate the validity of the proposed methodology. © 2014 IEEE.

关键词： Mobile cloud computing

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Modeling and Analysis of Mobile Cloud Computing Based on Bigraph Theory

Modeling and Analysis of Mobile Cloud Computing Based on Big...

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IEEE International Conference on Mobile Cloud Computing, Services, and Engineering

作者： Lian Yu Xin Wei Jerry Gao Wei Tek Tsai Xiao Qun Guo Thomas T. Hildebrandt School of Software & Microelectronics Peking University Dept. of Computer Engineering College of Engineering San Jose State University School of Comp. Info. and Dec. Systems Engineering Arizona State University Process and System Models Group IT University of Copenhagen

ISBN: (纸本)9781479944248

关键词： Mobile cloud Modeling and simulation Bigraphical reaction systems (BRSs) Sorting logic BRS-based simulation BRS-based MOF

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A reconfigurable routing method for fault-tolerant mesh-based network on chip

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Journal of Information and Computational Science 2013年第1期10卷 157-165页

作者： Liu, Yanhua Ruan, Ying Lai, Zongsheng Sun, Ling Institute of Microelectronics Circuit and System East China Normal University Shanghai 200241 China Jiangsu Provincial Key Lab. of ASIC Design Nantong University Nantong 226019 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

As the semiconductor industry advances to nano-technology points, Network on Chip (NoC) components are becoming vulnerable to errors during the system operation. Consequently, fault-tolerant techniques for NoC are needed to achieve high reliability. In this paper, we present a fault-tolerant routing method to tolerate faulty routers in a two-dimension (2D) mesh-based NoC. With this method, the system can have a multi-router fault-tolerant capability and the routing path can be dynamically reconfigured to support different situations caused by faulty routers in NoC. Fault-tolerance capability and system performance of the proposed method are evaluated through analysis and simulations. Theoretical analysis and simulation results show that the proposed method can enhance the reliability of system and offer considerable fault-tolerance capability. © 2013 by Binary Information Press.

关键词： Network-on-chip

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25th Annual Computational Neuroscience Meeting CNS-2016, Seogwipo City, South Korea, July 2-7, 2016 Abstracts

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BMC NEUROSCIENCE 2016年第1期17卷 1-112页

作者： [Anonymous] Computational Neurobiology Laboratory The Salk Institute for Biological Studies San Diego USA UNIC CNRS Gif sur Yvette France The European Institute for Theoretical Neuroscience (EITN) Paris France ATR Computational Neuroscience Laboratories Kyoto Japan Krembil Research Institute University Health Network Toronto Canada Department of Physiology University of Toronto Toronto Canada Department of Medicine (Neurology) University of Toronto Toronto Canada Department of Physics University of New Hampshire Durham USA Department of Neurophysiology Nencki Institute of Experimental Biology Warsaw Poland Department of Theory Wigner Research Centre for Physics of the Hungarian Academy of Sciences Budapest Hungary Department of Mathematical Sciences KAIST Daejoen Republic of Korea Department of Mathematics University of Houston Houston USA Department of Biochemistry & Cell Biology and Institute of Biosciences and Bioengineering Rice University Houston USA Department of Biology and Biochemistry University of Houston Houston USA Grupo de Neurocomputación Biológica Dpto. de Ingeniería Informática Escuela Politécnica Superior Universidad Autónoma de Madrid Madrid Spain Department of Biological Sciences University of Southern California Los Angeles USA Center for Neuroscience Korea Institute of Science and Technology Seoul South Korea Department of Neurology Albert Einstein College of Medicine Bronx USA Center for Neuroscience KIST Seoul South Korea Department of Neuroscience University of Science and Technology Daejon South Korea Systems Neuroscience Group QIMR Berghofer Medical Research Institute Herston Australia Department of Psychology Yonsei University Seoul South Korea Department of Psychiatry Kyung Hee University Hospital at Gangdong Seoul South Korea Department of Psychiatry Veterans Administration Boston Healthcare System and Harvard Medical School Brockton USA Department of Electrical and Electronic Engineering The University of Melbourne Parkvil

A1 Functional advantages of cell-type heterogeneity in neural circuits Tatyana O. Sharpee A2 Mesoscopic modeling of propagating waves in visual cortex Alain Destexhe A3 Dynamics and biomarkers of mental disorders Mitsuo Kawato F1 Precise recruitment of spiking output at theta frequencies requires dendritic h-channels in multi-compartment models of oriens-lacunosum/moleculare hippocampal interneurons Vladislav Sekulić, Frances K. Skinner F2 Kernel methods in reconstruction of current sources from extracellular potentials for single cells and the whole brains Daniel K. Wójcik, Chaitanya Chintaluri, Dorottya Cserpán, Zoltán Somogyvári F3 The synchronized periods depend on intracellular transcriptional repression mechanisms in circadian clocks. Jae Kyoung Kim, Zachary P. Kilpatrick, Matthew R. Bennett, Kresimir Josić O1 Assessing irregularity and coordination of spiking-bursting rhythms in central pattern generators Irene Elices, David Arroyo, Rafael Levi, Francisco B. Rodriguez, Pablo Varona O2 Regulation of top-down processing by cortically-projecting parvalbumin positive neurons in basal forebrain Eunjin Hwang, Bowon Kim, Hio-Been Han, Tae Kim, James T. McKenna, Ritchie E. Brown, Robert W. McCarley, Jee Hyun Choi O3 Modeling auditory stream segregation, build-up and bistability James Rankin, Pamela Osborn Popp, John Rinzel O4 Strong competition between tonotopic neural ensembles explains pitch-related dynamics of auditory cortex evoked fields Alejandro Tabas, André Rupp, Emili Balaguer-Ballester O5 A simple model of retinal response to multi-electrode stimulation Matias I. Maturana, David B. Grayden, Shaun L. Cloherty, Tatiana Kameneva, Michael R. Ibbotson, Hamish Meffin O6 Noise correlations in V4 area correlate with behavioral performance in visual discrimination task Veronika Koren, Timm Lochmann, Valentin Dragoi, Klaus Obermayer O7 Input-location dependent gain modulation in cerebellar nucleus neurons Maria Psarrou, Maria Schilstra, Neil Davey, Benjamin Torben-Ni

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Optimizing skyline queries in SPA distributed networks

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Tien Tzu Hsueh Pao/Acta Electronica Sinica 2013年第8期41卷 1515-1520页

作者： Huang, Zhen-Hua Xiang, Yang Sun, Sheng-Li Chen, Qian Department of Computer and Technology Tongji University Shanghai 201804 China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 201804 China School of Software and Microelectronics Peking University Beijing 102600 China

Skyline query has recently received a lot of attention in information service community. The TPAOSS (Three-Phase Algorithm for Optimizing Skyline Scalar) algorithm has two performance drawbacks: (1) in the third phase of TPAOSS, as the number of objects on net nodes increases, the length of bloom filter will increases exponentially, which will seriously influence the efficiency of obtaining replicated values and the occupation size of memory;(2) the TPAOSS algorithm does not consider the computation efficiency of local or global subspace skyline queries in each net node. Motivated by these facts, we propose EPSSQDN (Efficient Processing of Subspace Skyline Queries in Distributed Networks), an algorithm for efficient processing of subspace skyline queries in SPA distributed networks. Moreover, in order to further reduce the computation cost of subspace skyline queries and decrease the volume of data transferred, we present an efficient optimized techniques. Furthermore, we present extensive experiments that demonstrate our method is more advantageous than the TPAOSS algorithm.

关键词： Information services

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Design and optimization methodology for 3D RRAM arrays

Design and optimization methodology for 3D RRAM arrays

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International Electron Devices Meeting (IEDM)

作者： Yexin Deng Hong-Yu Chen Bin Gao Shimeng Yu Shih-Chieh Wu Liang Zhao Bing Chen Zizhen Jiang Xiaoyan Liu Tuo-Hung Hou Yoshio Nishi Jinfeng Kang H.-S. Philip Wong School of Electrical and Computer Engineering and Birck Nanotechnology Center Purdue University West Lafayette IN USA Department of Electrical Engineering and Center for Integrated Systems Stanford University Stanford CA USA Institute of Microelectronics Peking University Beijing China School of Computing Informatics and Decision System Engineering Arizona State University Tempe AZ USA Department of Electronics Engineering and Institute of Electronics National Chiao Tung University Hsinchu Taiwan Stanford University Stanford CA US

3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

关键词： Delays computer architecture Three-dimensional displays Microprocessors Energy consumption Tin Resistance

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