检索结果-内蒙古大学图书馆

IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Jacob N. Allen Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester Hills MI USA Air Force Research Laboratory OH USA

Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation. Opcodes sequence the control states and provide a vocabulary for assembly programs, which are compiled and executed on the microprocessor.

关键词： Microprocessors Hardware design languages Hardware XML Registers Fabrics Software

来源：评论

学校读者我要写书评

暂无评论

Case Studies on Transition Fault Test Generation for At-speed Scan Testing

Case Studies on Transition Fault Test Generation for At-spee...

引用

IEEE International Symposium on Defect and Fault Tolerance in VLSI systems

作者： Nor Azura Zakaria Edward V. Bautista Jr. Suhaimi Bahisham Jusoh Weng Fook Lee Xiaoqing Wen Microelectronics Technology Realisation and Operations MIMOS Berhad Kuala Lumpur Malaysia Emerald Systems Design Center Penang Malaysia Department of Creation Informatics Graduate School of Computer Science & System Engineering Kyushu Institute of Technology Iizuka Japan

At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and inter-clock domains for transition delay fault testing (i.e., intra-inter testing) is applied. This paper presents an empirical study by comparing between intra testing and intra-inter testing in terms of fault classification, test detection, test coverage, test volume, and test power by using industrial circuits. The information provided by this paper is beneficial to both practitioners and researchers in their pursuit of improving the quality of transition delay testing, which is critical to the quality of deep-sub micron VLSI chips.

关键词： Clocks Circuit faults Delay Synchronization Logic gates Automatic test pattern generation

来源：评论

学校读者我要写书评

暂无评论

Agile hardware development with rapid hardware definition language

Agile hardware development with rapid hardware definition la...

引用

IEEE International Conference on Electro-Information Technology

Rapid HDL is a hardware definition language developed in C# for the Microsoft .Net platform. Rapid HDL unifies digital FPGA hardware development and co-software integration. Hardware is scripted using reusable software objects, communication between hardware and software is automatic, and synthesis is automated using a free tool chain. Rapid HDL represents 18,000 lines of code and is freely available under the MIT license.

关键词： Hardware design languages Software libraries Testing Licenses microelectronics Force sensors Field programmable gate arrays Software reusability Software tools High level languages

来源：评论

学校读者我要写书评

暂无评论

Cognitive processing using spiking neural networks

Cognitive processing using spiking neural networks

引用

IEEE National Conference on Aerospace and Electronics (NAECON)

ISBN: (纸本)9781424444946

Powerful parallel cognitive processors can be developed by studying biologically plausible models of cognitive systems in animals and extrapolating key principles to be adapted for implementation in digital computer architectures. The network described here uses basic statistical methods such as proportion sampling on a massively parallel scale to create a general purpose pattern classifier. From these principles, we can achieve auto association and self organization that provides fundamental cognitive processing. Signal preprocessing is essential to transform the signal into a scale and rotation invariant binary pattern. The network avoids the curse of dimensionality by filtering out irrelevant inputs, allowing us to combine large sensor input vectors from multiple sources. Recent hardware designs define the network structure and state in memory, and then use accelerator processor cores to modify these memory structures in parallel.

关键词： Neural networks Neurons Biological system modeling Biology computing Biological information theory Brain modeling computer architecture microelectronics Power engineering and energy Biosensors

来源：评论

学校读者我要写书评

暂无评论

An Inter-MAC architecture for heterogeneous gigabit home networks

An Inter-MAC architecture for heterogeneous gigabit home net...

引用

IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Torsten Meyer Peter Langendörfer Michael Bahr Vincenzo Suraci Stefan Nowak Ralf Jennen Information & Communications Corporate Technology Siemens AG Munich Germany Department of System and Computer Science University of Roma La Sapienza Rome Italy System Design Innovations슠for슠High Performance Microelectronics Frankfurt Germany University of Rome Rome Italy RWTH Aachen University Aachen Germany

The home network of the near future will be a heterogeneous broadband network supporting the use of wired as well as wireless transmission technologies. The variety of services will range from HDTV via gaming to emergency services in the telemedicine area. In this paper, we introduce a technology-independent protocol layer called Inter-MAC which provides a common infrastructure to all home networking devices. The Inter-MAC can establish a connection via different transmission technologies while ensuring appropriate QoS. Key to this is the capability to correctly interpret technology-dependent PHY and MAC parameters for determining QoS when selecting initial and alternative paths, as well as the feature of admission control. Our simulations indicate clearly that the Inter-MAC approach can cope with varying loads, for instance, the time the jitter needed to stabilize was as short as 4 s. The reduced QoS was not noticeable by the user since the jitter introduced by handling additional HDTV flows was less than 0.2 ms for the existing and less than 0.7 ms for the new flow.

关键词： Home automation HDTV Jitter Broadband communication Emergency services Telemedicine Protocols Appropriate technology Physical layer Admission control

来源：评论

学校读者我要写书评

暂无评论

Deterministic Worst-Case Performance Analysis for Wireless Sensor Networks

Deterministic Worst-Case Performance Analysis for Wireless S...

引用

International Wireless Communications and Mobile Computing Conference, IWCMC

作者： Huimin She Zhonghai Lu Axel Jantsch Li-Rong Zheng Dian Zhou ASIC & System State Key Laboratory Department of Microelectronics Fudan University Shanghai China Department of Electronic Computer and Software Systems Royal Institute of Technology Sweden

ISBN: (纸本)9781424422012

Dimensioning wireless sensor networks requires formal methods to guarantee network performance and cost in any conditions. Based on network calculus, this paper presents a deterministic analysis method for evaluating the worst-case performance and buffer cost of sensor networks. To this end, we introduce three general traffic flow operators and derive their delay and buffer bounds. These operators are general because they can be used in combination to model any complex traffic flowing scenarios in sensor networks. Furthermore, our method integrates variable duty cycle to allow the sensor nodes to operate at lower rates thus saving power. Moreover, it incorporates traffic splitting mechanisms in order to balance network workload and nodes' buffers. To show how our method applies to real applications, we conduct a case study on a fresh food tracking application, which monitors the food freshness in realtime. The experimental results demonstrate that our method can be either used to perform network planning before deployment, or to conduct network reconfiguration after deployment.

关键词： Delay Wireless sensor networks Calculus Resource management Telecommunication traffic Bandwidth Base stations

来源：评论

学校读者我要写书评

暂无评论

An E-Nose Haar Wavelet Preprocessing Circuit for Spiking Neural Network Classification

An E-Nose Haar Wavelet Preprocessing Circuit for Spiking Neu...

引用

2008 IEEE International Symposium on Circuits and systems (ISCAS 2008), vol.7

作者： Jacob N. Allen Safa B. Hasan Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Lab Department of Elect. and Computer Engineering Oakland University MI USA Information Directorate Air Force Research Laboratories Wright Patterson Air Force Base OH USA

A simulation model for polymer film chemical sensors is developed based on a 1 dimensional diffusion equation. Using this model, electronic nose smell prints produced by the 32 sensor array of a Cyranose 320 are simulated to test pattern classification. A Haar wavelet filter reduces noise and captures information about the diffusion rate of the analyte in each sensor. Inputs are encoded into a binary Hamming pattern and fed into a binary spiking neural network for pattern classification. The preprocessing circuit for the spiking neural network, including the wavelet filter, is designed using standard cells for an 180nm process. Real and simulated results from the spiking neural network classification algorithm are favorably compared to Bayes, Canonical, and PCA-PNN classifiers.

关键词： Neural networks Circuit simulation Sensor arrays Chemical sensors Pattern classification Polymer films Equations Electronic noses Electronic equipment testing Circuit testing

来源：评论

学校读者我要写书评

暂无评论

Fractional-Order Signal Processing using a Polymer-Electrolyte Transistor

Fractional-Order Signal Processing using a Polymer-Electroly...

引用

51st Midwest Symposium on Circuits and systems (MWSCAS 2008), vol.2

作者： Robert L. Ewing Hoda S. Abdel-Aty-Zohdy Michael C. Hollenbeck Kenneth S. Stevens Information Directorate US Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Department of Electrical and Computer Engineering University of Utah Salt Lake UT USA

Fractional-order systems have applications in the areas of Flight Control, Robotics, Missile Guidance, Control of Structural Vibrations of Space Platforms and Sensor Technology. Fractional-order transfer functions can characterize complex nonlinear dynamics with many fewer parameters than integer-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating fractional-order algorithms for signal processing. The PET's advantage over the conventional RC and RL circuits is that it can be both functionally scaled and varied for dynamic fractional-order parameter controllability.

关键词： Fractional-Order Signal Processing Polymer-electrolyte transistor Acid/base chemistry Diffusion Electrokinetic flow

来源：评论

学校读者我要写书评

暂无评论

Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

引用

Journal of computer Science & Technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

来源：评论

学校读者我要写书评

暂无评论

Science Letters:A robust polysilicon-assisted SCR in ESD protection application

引用

Journal of Zhejiang University-Science A(Applied Physics & Engineering) 2007年第12期8卷 1879-1883页

作者： CUI Qiang HAN Yan DONG Shu-rong LIOU Juin-jie ESD Lab Institute of Microelectronics and Photoelectronics Zhejiang University Hangzhou 310027 China Research Center for Embedded System Zhejiang University Hangzhou 310027 China Department of Electrical and Computer Engineering University of Central Florida Orlando 32816 USA

A novel polysilicon-assisted silicon-controlled rectifier （SCR） is presented and analyzed in this paper, which is fabricated in HHNEC＇s 0.18μm EEPROM process. The polysilicon-assisted SCRs take advantage of polysilicon layer to help bypass electro-static discharge （E S D） current without occupying extra layout area. TLP current-voltage （I-V） measurement results show that given the same layout areas, robustness performance of polysilicon-assisted SCRs can be improved to 3 times of conventional MLSCR＇s. Moreover, one-finger such polysilicon-assisted SCRs, which occupy only 947 [3mz layout area, can undergo 7-kV HBM ESD stress. Results further demonstrate that the S-type I-V characteristics of polysilicon-assisted SCRs are adjustable to different operating conditions by changing the device dimensions. Compared with traditional SCRs, this new SCR can bypass more ESD currents and consumes smaller IC area.

关键词： Electro-static discharge （ESD） Silicon-controlled rectifier （SCR） Robustness performance Polysilicon-assisted Human body model （HBM）

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：