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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Ruiming Li Dian Zhou Jin Liu Xuan Zeng Department of Electrical Engineering School of Engineering and Computer Sciences University of Texas Dallas Richardson TX USA ASIC & System State-key Laboratory Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)0780388348

This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing. We obtain optimal solutions for the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS) under the delay constraints. These solutions can be used to estimate the power dissipation in the interconnect designs.

关键词： Wire Delay Power dissipation Capacitance Chromium MOS devices Circuits Threshold voltage Power engineering and energy Power engineering computing

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Long retention and low voltage operation using IrO2/HfAlO/HfSiO/ HfAlO gate stack for memory application

Long retention and low voltage operation using IrO2/HfAlO/Hf...

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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Wang, Y.Q. Singh, P.K. Yoo, W.J. Yeo, Y.C. Samudra, G. Chin, Albert Hwang, W.S. Chen, J.H. Wang, S.J. Kwong, D.-L. Silicon Nano Device Laboratory Dept. of Electrical and Computer Eng. National University of Singapore Singapore Singapore Dept. of Electro. Eng. Nat'1 Chiao Tung Univ. Univ. System of Taiwan Hsinchu Taiwan Institute of Mat'l. Res. and Eng. Singapore Singapore Institute of Microelectronics Singapore Singapore Univ. of Texas Austin United States

ISBN: (纸本)078039268X

We demonstrate electrical properties of an advanced memory structure with high-k dielectric stack of HfAlO/HfSiO/HfAlO and p-type metal gate IrO 2. Combining advantages of high-k HfAlO, good trapping capability of HfSiO, and high work function of the IrO2 gate, we were able to attain much better retention with 10-year ΔVth decay ratio within 18%, higher erasing speed with ΔVth, of 3V within 0.5ms at Vg = -12V, and lower operation voltage as well as lower reading voltage, compared to other contending device structures. © 2005 IEEE.

关键词： Gates (transistor)

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Long retention and low voltage operation using IrO/sub 2/HfAlO/HfSiO/HfalO gate stack for memory application

Long retention and low voltage operation using IrO/sub 2/HfA...

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International Electron Devices Meeting (IEDM)

作者： Y.Q. Wang P.K. Singh W.J. Yoo Y.C. Yeo G. Samudra A. Chin W.S. Hwang J.H. Chen S.J. Wang D.-L. Kwong Silicon Nano Device Laboratory Department of Electrical and Computer Engineering National University of Singapore Singapore Nano-Science Technology Center Department of Electro.Engineering National Chiao Tung University University System of Taiwan Hsinchu Taiwan Institute of Microelectronics Singapore University of Texas Austin USA

We demonstrate electrical properties of an advanced memory structure with high-k dielectric stack of HfAlO/HfSiO/HfXIO and p-type metal gate IrO 2 . Combining advantages of high-k HfAlO, good trapping capability of HfSiO, and high work function of the IrO 2 gate, we were able to attain much better retention with 10-year DeltaV th decay ratio within 18%, higher erasing speed with DeltaV th of 3V within 0.5ms at Vg equiv -12V, and lower operation voltage as well as lower reading voltage, compared to other contending device structures

关键词： Low voltage High-K gate dielectrics High K dielectric materials Annealing Hafnium oxide Tunneling Plasma properties Argon Sputtering Application software

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Digital domain time amplification in CMOS process

Digital domain time amplification in CMOS process

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Oulmane, Mourad Roberts, Gordon W. Microelectronics and Computer System Laboratory McGill University 3480 University Street Montreal H3A 2A7 Canada

In this paper the concept of time amplification in the digital domain is introduced along with simple CMOS implementations. Simulations suggest that the Time Amplifier (TAMP) can be practically designed for gains up to a few thousands with input dynamic ranges in excess of a few hundred picoseconds. Some figures of merit and performance are introduced along with a discussion on some of the trade-offs involved in the design of a Time Amplifier. © 2004 IEEE.

关键词： CMOS integrated circuits

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A CMOS time amplifier for Femto-second resolution timing measurement

A CMOS time amplifier for Femto-second resolution timing mea...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： M. Oulmane G.W. Roberts Microelectronics and Computer System Laboratory McGill University Montreal Canada

In this paper we present a new perspective on time amplification and its application to timing measurements on the Femto-second time scale. A simple yet practical circuit implementation for the amplification of the time between discrete (digital) events is introduced. Some metrics and figures of merit and performance are defined and parallels with the traditional amplification of "traditional physical" quantities, such as voltage and current, are drawn. The time amplifier (TAMP) has a dynamic range span from a few hundreds of Femto-seconds to a few hundreds of pico-seconds.

关键词： Time measurement Circuit testing Signal resolution system testing Transmission line measurements Timing jitter Voltage Differential amplifiers microelectronics Laboratories

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TeraHertz detectors based on plasma oscillations in nanometric Silicon Field Effect Transistors

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physica status solidi c 2005年第4期2卷

作者： F. Teppe Y. M. Meziani N. Dyakonova J. Łusakowski F. Bœuf T. Skotnicki D. Maude S. Rumyantsev M. S. Shur W. Knap GES CNRS-Université Montpellier 2 34900 Montpellier France ST Microelectronics BP 16 38921 Crolles France Grenoble High Magnetic Field Laboratory CNRS-MPI 38 450 Grenoble France Center for Broadband Data Transport Science and Technology and Electrical Computer and System Engineering Department Rensselaer Polytechnic Institute Troy New York 121180-3590 USA Ioffe Institute of Russian Academy of Sciences 194021 St. Petersburg Russia

We report on the experiments about detection of the THz radiation by silicon FETs with nanometer gate lengths. The observed photo-responses measured as a function of the gate voltage are all in agreement with the predictions of the Dyakonov-Shur theory. The plasma wave parameters deduced from the experiments allow us to predict also the possibility of resonant detection in THz range by nanometer size silicon devices. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

关键词： 73.20.Mf 85.30.Tv

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Effects of Noise and Jitter in Bandpass Sampling

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Analog Integrated Circuits and Signal Processing 2004年第1期42卷 85-97页

作者： Sun, Yi-Ran Signell, Svante Laboratory of Electronics and Computer System (LECS) Institute of Microelectronics and Information Technology (IMIT) Royal Institute of Technology (KTH) Stockholm Sweden

BandPass Sampling (BPS) is an undersampling technique by intentional aliasing. BPS enables one to have an interface between the IF stage and the ADC in a radio receiver. Conventional uniform BPS at Nyquist rate normally results in a low Signal-to-Noise Ratio (SNR) due to noise spectrum aliasing. The noise (e.g. kT/C noise introduced in a voltage-mode sampler) is combined in each of the Nyquist bands within the bandwidth of the sampling device. Also timing jitter causes a performance degradation in BPS. In this paper, signal spectrum aliasing, noise aliasing and jitter effects in BPS is analyzed. It is verified by simulation that NonUniform Sampling (NUS) has the potential to suppress signal spectrum aliasing and relax the requirement on the anti-aliasing (AA) filter. Jitter effects in BPS are compared to LowPass Sampling (LPS) case. However, a signal cannot be reconstructed from its nonuniform samples by using only ideal lowpass filtering (classic Shannon’s reconstruction). Finally, signal reconstruction in the presence of noise and jitter are investigated for three Reconstruction Algorithms (RAs) aimed at NUS.

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Effects of noise and jitter on algorithms for bandpass sampling in radio receivers

Effects of noise and jitter on algorithms for bandpass sampl...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yi-Ran Sun S. Signell Laboratory of Electronics and Computer System (LECS) Institute of Microelectronics and Information Technology (IMIT) Royal Institute of Technology Stockholm Sweden

Bandpass sampling (BPS) is an undersampling technique by intentional aliasing. Conventional uniform discrete sampling within an f/sub s/ band normally results in a bad signal-to-noise ratio (SNR) due to signal spectrum aliasing. The noise combined in each of the f/sub s/ bands below the highest frequency of the signal (the so called noise spectrum aliasing) and timing jitter are two causes of performance degradation in BPS system. Nonuniform BPS has the potential to suppress signal spectrum aliasing due to the aperiodic property of nonuniform sampling (NUS). In this paper, the frequency spectra of uniform sampling (US) and NUS are analyzed, signal spectrum aliasing, noise spectrum aliasing and jitter effects in BPS are studied. Finally, the performance of reconstruction algorithms (RAs) for nonuniform BPS in the presence of sources of performance degradation are discussed based on simulations.

关键词： Jitter Sampling methods Receivers Frequency Degradation Signal to noise ratio Signal analysis Signal sampling Radio communication Bandwidth

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Digital Domain Time Amplification in CMOS Process

Digital Domain Time Amplification in CMOS Process

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2004 7th International Conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Mourad Oulmane Gordon W.Roberts Microelectronics and Computer System Laboratory McGill University 3480 University StreetMontrealCanada H3A 2A7

In this paper the concept of time amplification in the digital domain is introduced along with simple CMOS *** suggest that the Time Amplifier(TAMP)can be practically designed for gains up to a few thousands with input dynamic ranges in excess of a few hundred *** figures of merit and performance are introduced along with a discussion on some of the trade-offs involved in the design of a Time Amplifier.

关键词： Digital Domain Time Amplification in CMOS Process

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Optimal ramped-gate soft programming of over-erased flash EEPROM cells at given current

Optimal ramped-gate soft programming of over-erased flash EE...

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Quan, Wu-Yun Baek, Chang-Ki Kim, Dae M. Gang, Ruan Huang, Yiping ASIC and System State-Key Research Lab. Department of Microelectronics Fudan University 220 Handan-road 200433 Shanghai China School of Electrical Engineering and Computer Science ISRC Seoul National University Kwanak P.O. Box 34 Seoul 151-744 Korea Republic of Korea Institute for Advanced Study 207-43 Cheongryangri Seoul Korea Republic of

Presented herein is an efficient simulation technique enabling systematic investigation of the soft programming over-erased flash EEPROM cells. The simulation provides a method by which to find the optimal soft programming technique for given current. The method requires only the cell performance data and allows investigation of the soft programming under various bias conditions. In principle, the methodology can also be used to investigate the programming and erase operations. © 2004 IEEE.

关键词： Flash memory

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