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Time partitioning framework for partially reconfigurable systems

Time partitioning framework for partially reconfigurable sys...

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International Conference on microelectronics, ICM

作者： A. Mtibaa B. Ouni M. Abid Nat. Eng. Sch. of Monastir Tunisia Laboratory of Electronics and Microelectronics University of Sciences of Monastir Tunisia Computer Electronic and Smart system Engineering National Engineering School of Sfax (ENIS) Tunisia

The FPGAs architectures allow the overlap between execution and reconfiguration. Indeed, fractions of the application can be configured at the same time that others fractions of the application can be executed. This approach is called partially reconfiguration that used for partially reconfigurable FPGAs. The partially reconfiguration approach can be used to fit a large application into the FPGA device by partitioning the application over time. At each partition, set of tasks are configured and other sets of tasks are executed. This partitioning over time of execution and configuration of tasks is achieved so that the latency of the application is optimal. In this paper, we introduce a time partitioning and a design flow approach for partially reconfigurable systems.

关键词： Field programmable gate arrays Flow graphs Delay Application software High level synthesis Partitioning algorithms Laboratories microelectronics systems engineering and theory computer architecture

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A versatile high speed bit error rate testing scheme

A versatile high speed bit error rate testing scheme

引用

IEEE International Symposium on Quality Electronic Design

作者： Yongquan Fan Z. Zeljko Man Wah Chiang Microelectronics and Computer System Laboratory McGill University Canada McGill University Montreal QC CA Microelectron. & Comput. Syst. Lab. McGill Univ. Montreal Que. Canada

The quality of a digital communication interface can be characterized by its bit error rate (BER) performance. To ensure the quality of the manufactured interface, it is critical to quickly and precisely test its BER behavior. Traditionally, BER is evaluated using software simulations, which are very time-consuming. Though there are some standalone BER test products, they are expensive and none of them includes channel emulators, which are essential to testing BER under the presence of noise. To overcome these problems, we present a versatile scheme for BER testing in FPGAs. This scheme consists of two intellectual property (IP) cores: the BER tester (BERT) core and the additive white Gaussian noise (AWGN) generator core. We demonstrate through case studies that the proposed solution exhibits advantages in speed and cost over existing solutions.

关键词： Bit error rate Testing Additive white noise AWGN Digital communication Manufacturing Gaussian noise Field programmable gate arrays Intellectual property Costs

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Detection of sub-Terahertz and Terahertz radiation by plasma waves in silicon field effect transistors

Detection of sub-Terahertz and Terahertz radiation by plasma...

引用

IEEE Sensors 2004

作者： Teppe, F. Meziani, Y. Dyakonova, N. Lusakowski, J. Knap, W. Bœuf, F. Skotnicki, T. Maude, D. Rumyantsev, S. Shur, M.S. Computer and System Engineering Department Rensselaer Polytechnic Institute Troy NY 12180-3590 United States Groupe d'Etude des Semi-Conducteurs UMR 5650 CNRS-Université Montpellier 2 Montpellier France ST Microelectronics BP 16 38921 Crolles France Grenoble High Magnetic Field Laboratory CNRS-MPI 38 450 Grenoble France Ioffe Institute of Russian Academy of Sciences 194021 St-Petersburg Russia

We report on the first experiments on detection of the sub-THz and THz (120 GHz and 3 THZ) radiation of Si FETs with nanometer and submicron gate lengths at 300K. The observed photo-response is in agreement with the predictions of Dyakonov-Shur theory. The plasma wave parameters deduced from the experiments allow us to predict the non resonant and resonant detection in THz range by nanometer size silicon devices. © 2004 IEEE.

关键词： Plasma waves

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Time partitioning framework for fully reconfigurable systems

Time partitioning framework for fully reconfigurable systems

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International Conference on microelectronics, ICM

作者： B. Ouni A. Mtibaa M. Abid Laboratory of Electronics and Microelectronics University of Sciences of Monastir Tunisia Lab. of Electron. & Microelectron. Univ. of Sci. of Monastir Tunisia Computer Electronic and Smart system Engineering National Engineering School of Sfax (ENIS) Tunisia

The SRAM technologies allow the FPGA device to be reconfigured by loading new configuration data. Real time reconfiguration can be performed by loading each configuration data then reinitializing the device. The entire process (loading and reinitializing) requires less than some milliseconds, which can be used to fit a large application onto the FPGA device by partitioning the application over time. Our first aim in this paper consists of introducing a design flow for reconfigurable systems, the second aim consists of introducing a time partitioning algorithm that divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal.

关键词： Field programmable gate arrays Data engineering Delay Algorithm design and analysis Partitioning algorithms Application software Costs Hardware Scheduling Optimal control

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Optimal ramped-gate soft programming of over-erased flash EEPROM cells at given current

Optimal ramped-gate soft programming of over-erased flash EE...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Wu-yun Quan Chang-Ki Baek D.M. Kim Ruan Gang Yiping Huang ASIC & System State-Key Research Laboratory Department of Microelectronics Fudan University Shanghai China School of Electrical Engineering and Computer Science and ISRC Seoul National University Seoul South Korea Korea Institute of Advanced Study Seoul South Korea

ISBN: (纸本)078038511X

Presented herein is an efficient simulation technique enabling systematic investigation of the soft programming over-erased flash EEPROM cells. The simulation provides a method by which to find the optimal soft programming technique for given current. The method requires only the cell performance data and allows investigation of the soft programming under various bias conditions. In principle, the methodology can also be used to investigate the programming and erase operations.

关键词： EPROM Threshold voltage Computational modeling microelectronics computer science Boosting Voltage control Charge pumps Testing Performance evaluation

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An artificial immune system strategy for robust chemical spectra classification via distributed heterogeneous sensors

An artificial immune system strategy for robust chemical spe...

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Congress on Evolutionary Computation

作者： M.A. Esslinger G.B. Lamont H.S. Abdel-Aty-Zohdy R.L. Ewing Department of Electrical and Computer Engineering Air Force Institute of Technology Dayton OH USA Microelectronics System Design Laboratory Oakland University Rochester MI Information Directorate Wright-Patterson AFB Air Force Research Laboratory Dayton Ohio USA

The timely detection and classification of biological agents in a hostile environment is critical for increasing protection in critical areas. This paper proposes a strategy for identifying biological agents via distributed sensors with an artificial immune system (AIS). The proposed system is composed of networked sensors and nodes, communicating via wireless or wired connections. Measurements are continually taken via dispersed redundant sensors strategically placed in threat areas. These sensors continually measure and categorize air or liquid samples, alerting surrounding nodes when possible biological agents are detected. Detection is based upon the biological immune system (BIS) model of antigens and antibodies, and alerts are generated when a measured sample is determined to be a valid biological agent (antigen). Biological agent signatures (antibodies) are continually distributed throughout the system to adapt to changes in the environment or to new antigens.

关键词： Chemical sensors Artificial immune systems Robustness Sensor systems Biosensors Chemical and biological sensors Wireless sensor networks Protection Wireless communication Area measurement

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Algorithms for nonuniform bandpass sampling in radio receiver

Algorithms for nonuniform bandpass sampling in radio receive...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yi-Ran Sun S. Signell Laboratory of Electronics and Computer System (LECS) Institute of Microelectronics and Information Technology (IMIT) Royal Institute of Technology Stockholm Sweden

The bandpass sampling (BPS) technique enables one to have an interface between IF stage and ADC in a radio receiver. Nonuniform BPS has the potential to suppress aliasing without care about the information band position of a modulated signal. However, a signal cannot be reconstructed from its nonuniform samples by using only an ideal lowpass filter. In this paper, a filter is generalized to a reconstruction algorithm (RA). Six different algorithms for reconstructing a signal from its nonuniform samples are summarized. A general reconstruction formula in terms of a basis-kernel (BK) function is used to describe the algorithms. Finally, with regard to the application to radio communications, accuracy of reconstruction, computational complexity and hardware implementation are shown and compared for these algorithms.

关键词： Sampling methods Receivers Image reconstruction RF signals Hardware Radio communication Computational complexity Bandwidth Low pass filters Interpolation

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Application of novel hierarchical approach to formal verification of digital ICs

Application of novel hierarchical approach to formal verific...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： F.A. El-Licy H.S. Abdel-Aty-Zohdy Department of Information and Computer Science Institute of Statistical Studies and Research Cairo University Egypt Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University MI USA

A hierarchical approach for the abstraction of digital VLSICs is presented. Circuit layout is hierarchically abstracted into logical constructs of binary tree structures, which may be manipulated to extract circuit functionality for the purpose of verifying design correctness. VLSIC design specification in the form of HDL is hierarchically decomposed to generate logical formulae for the given specification. By comparing the above, a verification report is obtained

关键词： Formal verification Logic design Binary trees Hardware design languages Production Very large scale integration Electrical capacitance tomography Combinational circuits Data structures Boolean functions

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On estimation of fault efficiency for path delay faults

On estimation of fault efficiency for path delay faults

引用

Asian Test Symposium (ATS)

作者： Fukunaga Kajihara Takeoka Graduate School of Computer Science and System Engineering Kyushu Institute of Technology Japan Center for Microelectronics Systems Kyushu Institute of Technology Japan Semiconductor Company Matsushita Elecrric Indusrrial Company Limited Japan

In this paper, we propose a method to estimate fault efficiency for path delay faults based on untestable path analysis. In path delay fault testing, fault coverage of test patterns is usually, very low, because logic circuits often have huge number of paths including many untestable paths. Hence we should compute fault efficiency rather than fault coverage, but it is too difficult to compute exact fault efficiency in a short time, because there is no method to compute total number of untestable paths quickly. The proposed method statistically estimate the number of untestable paths based on untestable path analysis, and compute fault efficiency. Experimental results show that the proposed method can accurately estimate fault efficiency of given test patterns in a reasonable time.

关键词： Logic circuit testing Fault diagnosis Combinational logic circuits Sequential logic circuits Very-large-scale integration

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Paradigm of design for biosystem-on-a-chip(BioSoC)

Paradigm of design for biosystem-on-a-chip(BioSoC)

引用

IEEE International Conference on Microelectronic systems Education

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy Information Directorate Air Force Research Laboratory Air Force Institute of Technology Department of Electrical and Computer Engineering Wright Patterson Air Force Base OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The paradigm of design for biosystem-on-a-chip (BioSoC), is that multidisciplinary skills are required. Thus, the educational goals are to develop an understanding of micro/macro collaboration along with the ability to apply and use multidisciplinary skills for the design and performance evaluation of a "biosystem on a chip". The need for the architectural design of the BioSoC addresses the next-generation of intelligent information processing systems.

关键词： Intelligent sensors Collaboration Design engineering Biology computing Chemical and biological sensors Biosensors Artificial intelligence microelectronics Circuits Chemical sensors

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