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Interprocedural side-effect analysis and optimisation in the presence of dynamic class loading

Interprocedural side-effect analysis and optimisation in the...

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28th Australasian computer Science Conference, ACSC 2005

作者： Hua, Phung Xue, Nguyen Jingling Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales Sydney NSW 2032 Australia

ISBN: (纸本)1920682201

We introduce a new approach to computing interprocedural modification side effects for Java programs in the presence of dynamic class loading. When compile-time unknown classes can be loaded dynamically, the points-to and modification sets computed statically based on the analysed program, called internal world, may be incomplete. Thus, the modification side effects cannot be determined based on such sets alone. We present a technique, called internal analysis (IA), to classify the references, objects and call sites in the analysed program so that we can determine which points-to and modification sets are deffinitely complete and which may be not. By combining the points-to sets and this classification, we obtain a new IA-based interprocedural side-effect analysis for determining the modification side-effects of any statement on any variable with good accuracy. We have implemented our algorithms in Soot. This paper demonstrates two important applications of this work: partial redundancy elimination (PRE) and copy propagation for field accesses. We report significantly increased opportunities in performing these optimisations over benchmarks when compared with a recently proposed technique in these areas. Our techniques are simple since they are flow-insensitive and achieve these improvements at small analysis costs. Copyright © 2005, Australian computer Society, Inc.

关键词： computer software

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Compiler-directed scratchpad memory management

Compiler-directed scratchpad memory management

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ICESS 2005 - 2nd International Conference on Embedded Software and Systems

作者： Jingling, Xue Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales Sydney NSW 2052 Australia

ISBN: (纸本)0769525121

On-chip memory, in the form of (hardware-managed) cache,(software-managed) scratchpad memory (SPM) or some combination of both, is widely used in embedded systems. Most high-end embedded systems have both cache and SPM on-chip since each addresses a different need. Caches allow easy integration and are often effective but are un-predictable. SPMs are more energy-efficient than caches since they do not need complex tag-decoding logic. In addition, SPMs provide absolutely predictable performance but the programmer or compiler must schedule explicit data/instruction transfers between the SPM and off-chip main memory in an embedded system. In today's industry, this task is largely accomplished manually. The programmer often spends a lot of time on partitioning data and/or instructions and inserting explicit data/instruction transfers required between the SPM and main memory. Such a manual approach is time-consuming and error-prone. Obtaining satisfactory solutions for large application programs by hand can be challenging. Furthermore, hand-crafted code is not portable since it is usually customized for one particular architecture. This talk introduces a compiler approach, called memory coloring that we have recently developed to automatically allocating the arrays in a program to an SPM. The arrays are frequently used in embedded applications such as image processing and signal processing. The novelty of this approach lies in partitioning an SPM into a pseudo register file, splitting the live ranges of arrays to create potential data transfer statements between the SPM and of-chip main memory, and finally, adapting an existing graph-colouring algorithm for register allocation to assign the arrays in the program into the register file. This compiler-directed approach is efficient due to the practical efficiency of graph-colouring algorithms. We have implemented this work in the SUIF/mach SUIF compiler framework. Preliminary results over benchmarks show that this compiler

关键词： Storage allocation (computer)

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Completeness analysis for incomplete object-oriented programs

Completeness analysis for incomplete object-oriented program...

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14th International Conference on Compiler Construction, CC 2005, held as part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005

作者： Xue, Jingling Nguyen, Phung Hua Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales Sydney NSW 2032 Australia

We introduce a new approach, called completeness analysis, to computing points-to sets for incomplete Java programs such as library modules or applications in the presence of dynamic class loading. One distinctive feature of this work is that the access and modification properties of fields are taken into account. By combining with a whole-program points-to analysis, completeness analysis yields not only the required points-to sets but also determines which points-to sets and call sites are complete (when the pointed-to objects and target methods are statically resolvable) or not. Such a compositional approach yields more precise points-to sets than those computed by the points-to analysis alone. In addition, our technique also determines (for the first time) which objects may be incompletely detectable, i.e., may be missing in some statically computed points-to sets. We provide experimental evidence to demonstrate that better analysis precision in benchmarks is obtained when the field access and modification properties are exploited. In particular, we are able to find significantly more complete and mono call sites in an incomplete program, which is useful in devirtualisation and inlining. Our analysis is simple since it is flow- and context-insensitive and achieves these improvements at reasonably small analysis costs. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Object oriented programming

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Personalizing and discussing algorithms within CS1 studio experiences: An observational study 05

Personalizing and discussing algorithms within CS1 studio ex...

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1st International Computing Education Research Workshop, ICER 2005

作者： Hundhausen, Christopher D. Brown, Jonathan Lee Visualization and End User Programming Lab School of Electrical Engineering and Computer Science Washington State University Pullman WA 99164-2752

ISBN: (纸本)1595930434

Pedagogical algorithm visualization technology aims to assist learners in understanding the dynamic behavior of computer algorithms. A key trend in past experimental studies is that learners benefit most when they are actively engaged with algorithm visualization technology. Inspired by this trend, we are exploring the pedagogical value of a novel active learning activity - the Studio Experience - within the context of an introductory CS1 unit on algorithmic problem-solving. In a Studio Experience, student pairs are given algorithm design problems, e.g., "design two alternative algorithms that reverse the values in a list." They are tasked both with constructing algorithmic solutions and accompanying visualizations, and with presenting their visualizations for feedback and discussion in a session modeled after an architectural "design crit." Through an observational study of studio experience sessions in which students used two alternative forms of visualization technology -art supplies and a computer-based tool - we gained insight into (a) the processes by which students construct visual presentations of algorithms, (b) the characteristics of their visual presentations;(c) the nature of conversations mediated by visual algorithmic solutions;and (d) the kind of visualization technology that best supports these activities. Based on our results, we suggest improvements to the approach, and propose an agenda for future empirical studies. Copyright 2004 ACM.

关键词： computer science

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A dynamic compilation framework for controlling microprocessor energy and performance 38

A dynamic compilation framework for controlling microprocess...

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MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Wu, Qiang Reddi, V.J. Wu, Youfeng Lee, Jin Connors, Dan Brooks, David Martonosi, Margaret Clark, Douglas W. Depts. of Computer Science Electrical Engjneering Princeton University Dept. of Electrical and Computer Engineering U. of Colorado Boulder Programming Systems Lab. Corporate Tech. Group Intel Corporation Division of Engineering and Applied Science Harvard University

ISBN: (纸本)0769524400

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrialstrength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3X-5X better than static voltage scaling, and is more than 2X (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control. © 2005 IEEE.

关键词： Microprocessor chips

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The use of a Reasoning process to solve the almost SLAM Challenge at the Robocup legged league

The use of a Reasoning process to solve the almost SLAM Chal...

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8th Catalan Conference on Artificial Intelligence, CCIA 2005

作者： Monferrer, M. Teresa Escrig Broch, Juan Carlos Peris Jaume I University Engineering and Computer Science Department Campus Riu Sec CastellónE-12071 Spain Jaume I University Programming Languages and Computer Systems Department Campus Riu Sec CastellónE-12071 Spain

ISBN: (纸本)1586035606

The problem that a robot navigates autonomously through its environment, builds its own map and localizes itself in the map (known a the SLAM problem), is still an open problem. Most of the approaches to solve the SLAM problem divide the space into regions and compute the probability that the robot is in each region. We propose in this paper a different solution based on the use of a reasoning process to build the map, which will provide the following advantages: (1) we will store in the map hybrid (qualitative + quantitative) information from landmarks. Qualitative representation will allow us the management of the uncertainty information provided by the robot sensors;and (2) we will store in the map relative information of the landmarks which appear in the environment, therefore the map will be independent of the point of view of the robot. Moreover, we are going to use a reasoning process which will allow us to solve three very important problems in robotics: (a) where the robot is;(b) which is the orientation of the map where the robot is;and (c) towards where the robot should go according to the map to follow a plan. © 2005 The authors. All rights reserved.

关键词： Robots

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What you see is what you code: a radically dynamic algorithm visualization development model for novice learners

What you see is what you code: a radically dynamic algorithm...

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IEEE Symposium on Visual Languages and Human Centric Computing (VL/HCC)

作者： C.D. Hundhausen J.L. Brown Visualization and End User Programming Laboratory School of Electrical Engineering and Computer Science Washington State University Pullman WA USA

Pedagogical algorithm visualization systems produce graphical representations that aim to assist learners in understanding the dynamic behavior of computer algorithms. In order to foster active learning, educators have explored algorithm visualization systems that empower learners to construct their own visualizations of algorithms under study. Notably, these systems support a similar development model in which coding the algorithm is temporally distinct from viewing and interacting with the resulting visualization. To explore the benefits of narrowing the gap between coding an algorithm and viewing its visualization, we have implemented "What You See Is What You Code", a novel, "radically dynamic" development model to facilitate learner-constructed algorithm visualizations. In this model, the line of algorithm code currently being edited is reevaluated on every edit, leading to the dynamic update of an accompanying visualization of the algorithm. Analysis of usability studies involving introductory computer science students suggests that the immediacy of the model's feedback can help novices to quickly identify and correct programming errors, and ultimately to understand their code's execution.

关键词： Heuristic algorithms Visualization Feedback computer science programming profession Writing Dynamic programming Usability computer errors Laboratories

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A dynamic compilation framework for controlling microprocessor energy and performance

A dynamic compilation framework for controlling microprocess...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Qiang Wu V.J. Reddi Youfeng Wu Jin Lee D. Connors D. Brooks M. Martonosi D.W. Clark Depts. of Computer Science Electrical Engineering Princeton University USA Department of Electrical and Computer Engineering University of Colorado Boulder USA Programming Systems Laboratory Intel Corporation USA Division of Engineering and Applied Science Harvard University USA

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control

关键词： Dynamic compiler Microprocessors Performance loss Voltage control Hardware Energy measurement Dynamic voltage scaling Frequency Energy management Microarchitecture

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Automatic discovery of translation collocations from bilingual corpora 16

Automatic discovery of translation collocations from bilingu...

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16th European Conference on Artificial Intelligence, ECAI 2004

作者： Barrachina, Sergio Vilar, Juan Miguel Dpt. of Computer Engineering and Science Universitat Jaume I Castellón Spain Dpt. of Programming Languages and Computer Systems Universitat Jaume I Castellón Spain

ISBN: (纸本)9781586034528

We describe a method to automatically discover translation collocations from a bilingual corpus and how these improve a machine translation system. The process of inference of collocations is iterative: An alignment is used to derive an initial set of collocations, these are used in turn to improve the alignment and this new alignment is used to generate new collocations. This process is repeated until no more collocations are found. The final alignment and the set of collocations are used to train a translation model. We use a model that is based on finite state transducers and word clusters and has been modified to work with collocations in addition to single words. We present experiments in which we show that automatic collocations improve translation quality without prior linguistic information.

关键词： Alignment

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Optimised asynchronous self-timing for superconducting RSFQ logic circuits

Optimised asynchronous self-timing for superconducting RSFQ ...

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AFRICON Conference

作者： H.R. Gerber C.J. Fourie W.J. Perold Applied computer programming and computer systems Electronics and quantum electronics Department of Electronic and Electrical Engineering University of Stellenbosch

Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested

关键词： Superconducting logic circuits Logic circuits Clocks Timing Logic testing Digital circuits Logic gates Design methodology Circuit testing Adders

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