The incorporation of wind power generation to the power system leads to an increase in the variability of the system power flows. The assessment of this variability is necessary for the planning of the necessary syste...
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The incorporation of wind power generation to the power system leads to an increase in the variability of the system power flows. The assessment of this variability is necessary for the planning of the necessary system reinforcements. For the assessment of this variability, the uncertainty in the system inputs should be modeled, comprising of the time-dependent stochasticity of the system loads and the correlated wind resources. In this contribution, a unified Monte-Carlo simulation methodology is presented that addresses both issues. The application of the method for the analysis of the wind power integration in the New England test system is presented.
An 81.6 GOPS object recognition processor is developed by using NoC and Visual Image Processing (VIP) memory. SIFT (Scale Invariant Feature Transform) object recognition requires huge computing power and data transact...
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An 81.6 GOPS object recognition processor is developed by using NoC and Visual Image Processing (VIP) memory. SIFT (Scale Invariant Feature Transform) object recognition requires huge computing power and data transactions among tasks. The chip integrates 10 SIMD PEs for data/task level parallelism while the NoC facilitates inter-PE communications. The VIP memory searches local maximum pixel inside a 3×3 window in a single cycle providing 65.6 GOPS. The proposed processor achieves 15.9fps SIFT feature extraction at 200MHz.
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together wit...
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This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their impact on the PPM level. The preliminary silicon results are presented and analyzed. They validate some of the new dynamic fault models and show the importance of considering dynamic faults for high outgoing product quality.
An 81.6 GOPS object recognition processor based on memory-centric NoC (MC-NoC) is implemented in a 0.18-mum CMOS technology. The MC-NoC facilitates data transactions among 10 SIMD processing elements (PEs) by exploiti...
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An 81.6 GOPS object recognition processor based on memory-centric NoC (MC-NoC) is implemented in a 0.18-mum CMOS technology. The MC-NoC facilitates data transactions among 10 SIMD processing elements (PEs) by exploiting 8 visual image processing (VIP) memories. The 10 PEs implement special SIMD instructions to perform Gaussian filtering at 16 GOPS. The 8 VIP memories provide one cycle local maximum pixels search operation performing 65.6 GOPS. The chip dissipates 1.4 W at 200 MHz operating frequency.
A high-frequency transmitter has been designed for high data-rate biomedical telemetry. Although high frequencies face greater attenuation, transcutaneous transmission was successfully tested and verified using a 3.76...
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A high-frequency transmitter has been designed for high data-rate biomedical telemetry. Although high frequencies face greater attenuation, transcutaneous transmission was successfully tested and verified using a 3.76mm thick sample of porcine skin. The structure transmits over 440μW of power, consumes about 4.9mA of current from a 1.8V supply, and achieves a phase noise of -72dBc/Hz at 100KHz. The transmitter operates at around 6.7GHz with a 50MHz tuning range and is fully integrated on the CMOS IBM7RF 0.18μm process.
This paper presents new quasi-static single-phase energy recovery logic (QSSERL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock without additional voltages. This not only ...
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This paper presents new quasi-static single-phase energy recovery logic (QSSERL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock without additional voltages. This not only ensures lower energy dissipation, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. HSPICE simulation with an 8-bit logarithmic lookahead adder (LLA) using static CMOS, CAL (an existing single-phase based energy recovery logic), and QSSERL shows that the QSSERL adder consumes only 56% of energy as with its static CMOS counterpart at 10MHz and achieves better energy efficiency than CAL.
This paper presents a new quasi-static single-phase energy recovery logic (QSSERL), which unlike any other existing adiabatic logic family, uses a single sinusoidal supply-clock without additional timing control volta...
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This paper presents a new quasi-static single-phase energy recovery logic (QSSERL), which unlike any other existing adiabatic logic family, uses a single sinusoidal supply-clock without additional timing control voltages. This not only ensures lower energy dissipation, but also simplifies the clock design, which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. Simulation with an 8bit logarithmic look-ahead adder (LLA) using static CMOS, clocked CMOS adiabatic logic (CAL, an existing typical single-phase energy recovery logic), and QSSERL, under 128 randomly generated input vectors, shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10 MHz, and the QSSERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2 MHz.
作者:
Jimshone LiJason Sheng-Hong TsaiLeang-San ShiehControl System Laboratory
Department of Electrical Engineering National Cheng Kung University Tainan 701 Taiwan R.O.C. Jim-Shone Li was born in Taiwan
R. O.C. on April 20 1967. He received B.S. and M.S. degrees in Electrical Engineering from the Chung-Cheng Institute of Technology Taoyuan Taiwan R.O.C. in 1989 and 1993 respectively. He is currently a Ph.D. student at National Cheng-Kung University Tainan Taiwan R.O.C. His research interests include analysis and design of multidimensional systems and nonlinear system control. Department of Electrical and Computer Engineering
University of Houston Houston TX 77004-4793 U.S.A.
An optimal control method for two-dimensional (2-D) linear systems with variable coefficients and free boundary conditions in Roesser's model is proposed in this paper. Based on Roesser's model, an equivalent ...
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An optimal control method for two-dimensional (2-D) linear systems with variable coefficients and free boundary conditions in Roesser's model is proposed in this paper. Based on Roesser's model, an equivalent general 1-D model of the 2-D system is presented, and the problem of minimizing a 2-D linear quadratic (LQ) cost function is solved for the case where complete state information is available. The solution is obtained by using the proposed dynamic programming in 1-D descriptor form to solve the Riccati equation and then arriving at the optimal control law and minimum cost. The proposed control methodology can be applied to discrete-time models of systems described by partial differential equations and can also be used in the field of signal processing.
Different from the traditional wireless networks, in wireless sensor networks(WSNs) , power consumption is a critical aspect, because current nodes are always supported by constrained-energy battery. A particular chal...
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Different from the traditional wireless networks, in wireless sensor networks(WSNs) , power consumption is a critical aspect, because current nodes are always supported by constrained-energy battery. A particular challenge in maintaining extended battery lifetime lies in achieving communications with low power. For better understanding of the design trade offs of WSNs, a more accurate power consumption model for wireless sensor node is proposed. Different from models ever showed, in which the power consumption of each component in WSN node was assumed constant , the new one takes into account energy dissipation of circuits in practical physical layer. It shows that there are some parameters such as data rate, carrier frequency, RF output power et al, which have a significant effect on the WSN node with the metric energy per useful bit (EPUB). Then an optimal design method to make the network energy efficient is described by adjusting one or more of these parameters. The efficiency of the strategy was validated by mathematical analysis and simulations. The results showed that the EPUB can be reduced by optimally choosing the rate-power combination based on the proposed power consumption model for a given load.
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