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Biologically-Based Signal Processing Chips with Emphasis on Telecommunication Defect Tracking and Reliability Estimation

Biologically-Based Signal Processing Chips with Emphasis on ...

引用

IEEE Pacific Rim Conference on Communications, computers and Signal Processing

作者： Hoda S Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester MI USA

This paper provides observations and motivations to mimic biological information processing. Alternative bio-inspired systems definitions, basics, approaches, algorithms, and chip implementations will be illustrated to offer a base of choice for bio-based Intelligent Information Processing (IIP) systems. Hybrid biological and bio-based IIP are briefly presented. Two specific applications follow with embedded bio-based systems: Bio-chemical sensing and detection E-nose; and Track improvements In the reliability of the software used in telecommunication network deployments. The biologically-based processing discoveries gleaned from observing the spikes in the brain activity of monkeys, introduced the concept of plasticity in synapses used in our embedded Spiking Neural Network (SNN) system for the E-Nose The mathematical construct of a defect tracking classifier is nonlinear, and the event to be recognized involves a sequentially varying or non-stationary phenomenon for telecommunication defect tracking and reliability estimation. Thus, Adaptive Recurrent Dynamic Neural Network (ARDNN) system using wavelet function as the basis improved the failure event estimation of software defect tracking in telecommunications and reduced the error from 88% to L25-8%.

关键词： Biomedical signal processing Signal processing algorithms Information processing Telecommunication network reliability Biological neural networks Application software Embedded software Brain Nonlinear dynamical systems Neural networks

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On-Line Dynamic Voltage Scaling on Processor with Discrete Frequency and Voltage Levels

On-Line Dynamic Voltage Scaling on Processor with Discrete F...

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International Conference on Convergence Information Technology

作者： Min-Sik Gong Yeong Rak Seong Cheol-Hoon Lee System Software Laboratory Department of Computer Engineering Chungnam National University Daejeon South Korea Computer Engineering Laboratory School of Electrical Engineering Kookmin University Seoul South Korea Department of Computer Engineering Chungbuk National University Daejeon South Korea

ISBN: (纸本)9780769530383

The processors supporting the dynamic voltage scaling, called by DVS, have a feature that practically operates with discrete frequency and voltage levels. Almost of DVS algorithms select the smallest frequency level greater than the computed ideal level. Thus the system wastes a computational resource due to under-utilization. In this paper, we present an approach that the task executes its job under two adjacent discrete frequency levels, if possible, instead of the scaling factor computed by on-line dynamic voltage scaling(OLDVS) under the ideal level. This approach combines discrete DVS feature with OLDVS. So, each task can divide the given time budgets into two parts. Then the task executes its job at the lower frequency/voltage level in the first part. If the task does not complete until the end of the first part, then the scheduler increases the frequency to complete the remaining computation load with the remaining time budgets. Therefore, it can achieve more energy savings than the original OLDVS while simultaneously preserving timeliness guarantees made by real-time scheduling. Simulation results show that OLDVS provides up to 20% of additional energy savings for Intel PXA250[18] which has four discrete frequency/voltage levels.

关键词： Dynamic voltage scaling Frequency Voltage control Real time systems Processor scheduling system software Portable computers Clocks Scheduling algorithm Switches

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A Framework for Providing Quality of Service in Chip Multi-Processors 40

A Framework for Providing Quality of Service in Chip Multi-P...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Fei Guo Yan Solihin Li Zhao Ravishankar Iyer Department of Electrical and Computer Engineering North Carolina State University USA System Technology Laboratory Intel Corporation USA

ISBN: (纸本)9780769530475

The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse in terms of performance, reliability, and availability requirements. It can be expected that more and more applications with diverse requirements will run on a CMP and share platform resources such as the lowest level cache and off-chip bandwidth. In this environment, it is desirable to have microarchitecture and software support that can provide a guarantee of a certain level of performance, which we refer to as performance Quality of Service. In this paper, we investigate a framework that would be needed for a CMP to fully provide QoS. We found that the ability of a CMP to partition platform resources alone is not sufficient for fully providing QoS. We also need an appropriate way to specify a QoS target, and an admission control policy that accepts jobs only when their QoS targets can be satisfied. We also found that providing strict QoS often leads to a significant reduction in throughput due to resource fragmentation. We propose novel throughput optimization techniques that include: (1) exploiting various QoS execution modes, and (2) a microarchitecture technique that steals excess resources from a job while still meeting its QoS target. We evaluated our QoS framework with a full system simulation of a 4-core CMP and a recent version of the Linux Operating system. We found that compared to an unoptimized scheme, the throughput can be improved by up to 47%, making the throughput significantly closer to a non-QoS CMP.

关键词： Quality of service Throughput Microarchitecture Availability Application software Bandwidth Software performance Software quality Admission control Linux

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Intelligent Data Analysis for Diagnostics of Alcohol Dependency

Intelligent Data Analysis for Diagnostics of Alcohol Depende...

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Annual IEEE Symposium on computer-Based Medical systems

作者： Petra Povalej Matej Kravos Peter Kokol Laboratory for System Design Faculty of Electrical Engineering and Computer Science University of Maribor Slovenia Psychiatric Hospital Ormož Ormoz Slovenia

The alcohol dependency is hard to diagnose since none of the existing laboratory markers has sufficient specificity and sensitivity. Therefore the goal of our study was to find better laboratory markers and / or their combinations. For that purpose the intelligent data analysis using the decision tree induction method was used. The results show that the combination of three or even two markers can prove alcohol dependency with almost 85% accuracy. However the remark has to be made that the induced decision tree offers a qualitatively different access to diagnostic evaluation of laboratory findings and varies from common practice, because it sets up its new and own borders and criteria what is the unlike from generally accepted or set up reference values. All selected markers are widely accessible, inexpensive and part of a routine laboratory tests.

关键词： Data analysis Laboratories Decision trees Medical diagnostic imaging Alcoholism Testing Biochemistry Databases Decision making Learning systems

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Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC

Solutions for Real Chip Implementation Issues of NoC and The...

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International Symposium on Networks-on-Chip (NOCS)

作者： Donghyun Kim Kwanho Kim Joo-Young Kim Seung-Jin Lee Hoi-Jun Yoo Semiconductor System Laboratory Department of Electronic Engineering and Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

This paper describes real chip implementation issues of network-on-chip (NoC) and their solutions along with series of chip design examples. The solutions described in this paper cover both architectural aspects and circuit level techniques for practical chip implementation of NoC. As for architecture level solutions, topology selection, chip-aware protocol design, and on-chip serialization (OCS) for link area reduction are explained. For circuit level techniques, SERDES and synchronizer design, crossbar switch partial activation, and low-voltage link are presented as the foundations for power and area efficient NoC implementation. Regarding presented solutions for NoC implementation, this paper proposes memory centric NoC (MC-NoC) for homogeneous multi processor SoC (MPSoC). Flexibility and feasibility of task mapping on homogeneous SoC is the key feature of the MC-NoC. 8 dual port SRAMs connected to crossbar switches in hierarchical star topology network facilitate data communication between processors, regardless of task mapping into the MC-NoC. Experimental result obtained by mapping edge detection tasks on the MC-NoC in various configurations shows almost constant performance. This result proves the effectiveness of the proposed architecture. The MC-NoC based SoC is also implemented on TSMC 0.18 um process technology

关键词： Network-on-a-chip Switches Network topology Chip scale packaging Circuit topology Protocols Switching circuits Communication switching Data communication Image edge detection

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Estimation of Power system Variability due to Wind Power

Estimation of Power System Variability due to Wind Power

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Power Tech Conference

作者： George Papaefthymiou Jody Verboomen Lou van der Sluis Electrical Power System Laboratory (EPS) Faculty of Electrical Engineering Mathematics ' Computer Science Delft University of Technnology Delft Netherlands

The incorporation of wind power generation to the power system leads to an increase in the variability of the system power flows. The assessment of this variability is necessary for the planning of the necessary system reinforcements. For the assessment of this variability, the uncertainty in the system inputs should be modeled, comprising of the time-dependent stochasticity of the system loads and the correlated wind resources. In this contribution, a unified Monte-Carlo simulation methodology is presented that addresses both issues. The application of the method for the analysis of the wind power integration in the New England test system is presented.

关键词： Power systems Wind energy Power system modeling Wind energy generation Wind power generation Load flow Wind speed Stochastic systems Power generation Power system planning

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An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory

An 81.6 GOPS Object Recognition Processor Based on NoC and V...

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29th Annual IEEE Custom Integrated Circuits Conference (CICC 2007), vol.2

作者： Donghyun Kim Kwanho Kim Joo-Young Kim Seungjin Lee Hoi-Jun Yoo Semiconductor System Laboratory Department of Electronic Engineering and Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

An 81.6 GOPS object recognition processor is developed by using NoC and Visual Image Processing (VIP) memory. SIFT (Scale Invariant Feature Transform) object recognition requires huge computing power and data transactions among tasks. The chip integrates 10 SIMD PEs for data/task level parallelism while the NoC facilitates inter-PE communications. The VIP memory searches local maximum pixel inside a 3×3 window in a single cycle providing 65.6 GOPS. The proposed processor achieves 15.9fps SIFT feature extraction at 200MHz.

关键词： Object recognition Network-on-a-chip Image processing Parallel processing Vehicle detection computer architecture Intelligent robots Concurrent computing Filtering Energy consumption

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PPM Reduction on Embedded Memories in system on Chip

PPM Reduction on Embedded Memories in System on Chip

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IEEE European Test Symposium (ETS)

作者： Said Hamdioui Zaid Al-Ars Javier Jimenez Jose Calero Computer Engineering Laboratory Delft University of Technnology Delft Netherlands Design of System on Silicon (DS2) Valencia Spain

This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their impact on the PPM level. The preliminary silicon results are presented and analyzed. They validate some of the new dynamic fault models and show the importance of considering dynamic faults for high outgoing product quality.

关键词： system-on-a-chip Circuit faults Silicon system testing Random access memory Decoding Fault detection Delay Stress Circuit testing

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Implementation of Memory-Centric NoC for 81.6 GOPS object recognition processor

Implementation of Memory-Centric NoC for 81.6 GOPS object re...

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IEEE Asian Conference on Solid-State Circuits (ASSCC)

作者： Donghyun Kim Kwanho Kim Joo-Young Kim Seungjin Lee Hoi-Jun Yoo Semiconductor System Laboratory Department of Electronics Engineering and Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

An 81.6 GOPS object recognition processor based on memory-centric NoC (MC-NoC) is implemented in a 0.18-mum CMOS technology. The MC-NoC facilitates data transactions among 10 SIMD processing elements (PEs) by exploiting 8 visual image processing (VIP) memories. The 10 PEs implement special SIMD instructions to perform Gaussian filtering at 16 GOPS. The 8 VIP memories provide one cycle local maximum pixels search operation performing 65.6 GOPS. The chip dissipates 1.4 W at 200 MHz operating frequency.

关键词： Network-on-a-chip Object recognition Parallel processing CMOS technology Image processing Intelligent robots Energy consumption Pixel Memory management Communication channels

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High Data-Rate 6.7GHz Wireless ASIC Transmitter for Neural Prostheses

High Data-Rate 6.7GHz Wireless ASIC Transmitter for Neural P...

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29th Annual International Conference of the IEEE engineering in Medicine and Biology Society (EMBS 2007), vol.16

作者： Eric Y. Chow Adam Kahn Pedro P. Irazoqui Brain Computer Interface Laboratory Weldon School of Biomedical Engineering and School of Electrical and Computer Engineering Purdue University West Lafayette IN USA Purdue University System West Lafayette IN US Brain Computer Interface Laboratory Weldon School of Biomedical Engineering Purdue University West Lafayette IN USA

A high-frequency transmitter has been designed for high data-rate biomedical telemetry. Although high frequencies face greater attenuation, transcutaneous transmission was successfully tested and verified using a 3.76mm thick sample of porcine skin. The structure transmits over 440μW of power, consumes about 4.9mA of current from a 1.8V supply, and achieves a phase noise of -72dBc/Hz at 100KHz. The transmitter operates at around 6.7GHz with a 50MHz tuning range and is fully integrated on the CMOS IBM7RF 0.18μm process.

关键词： Application specific integrated circuits Neurotransmitters Prosthetics Transmitters Biomedical telemetry Frequency Attenuation Testing Skin Phase noise

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