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International Symposium on Telecommunications (BIHTEL)

作者： Emil Gracic Ali Hayek Josef Börcsök Chair for Computer Architecture and System Programming University of Kassel Kassel Germany

This paper describes the implementation and integration process of a complete communication computer system on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated to achieve a safety-related architecture. For this purpose a diagnostic unit will be implemented, consisting of hardware and software tests. Hardware tests are related to the control of the FPGA functionality. They are based on the integration of two existing methods to reach complete hardware test coverage. The software tests are used for a continuous testing of the whole system (this means testing the central processing unit, bus systems, peripherals and memory). Furthermore, a safety multiplexer is integrated with the task to turn off the current operating system (main system) and to turn on a redundant system when a failure is introduced via the diagnostic unit. The safety multiplexer has to give the permission to the redundant system to receive the outputs from the main system in a way that is free from faults. The microcontroller ColdFire is used as a basis, which provides numerous features for the control of various peripherals as well as the connection of various types of memory.

关键词： Safety Field programmable gate arrays Multiplexing computers Hardware Software Microcontrollers

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Evaluation and analysis of an on-chip safety system architecture

Evaluation and analysis of an on-chip safety system architec...

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IEEE SSD International Multi-Conference on systems, Signals and Devices

作者： Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual components of a target control system can be integrated into a single silicon die at lowest level, which in turn contributes in saving the substantial space and reduces power consumption and production costs. With the consideration of the miniaturization of safety-related systems into system-on-chips, where usually complete redundant architectures along with memories and interfaces are integrated into small silicon structures, many advantages can be taken into account. These advantages extend to all levels of the development cycle. In the present paper, a concept for on-chip safety system architecture is presented briefly. Primarily, a qualitative evaluation and analysis of the presented architecture is explicitly focused and discussed. The evaluation and analysis is based on a comparison to a similar conventional discrete safety-related architecture.

关键词： Reliability Sensors computer architecture Service-oriented architecture Safety Actuators Monitoring

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On-chip safety system for embedded control applications

On-chip safety system for embedded control applications

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Mediterranean Electrotechnical Conference (MELECON)

作者： Ali Hayek Josef Börcsök Chair for Computer Architecture and System Programming University of Kassel Kassel Germany

In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.

关键词： Safety system-on-chip computer architecture IEC standards Hardware Software

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RAM tests for safety-related architectures: A first approach

RAM tests for safety-related architectures: A first approach

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International Symposium on Fundamentals of Electrical Engineering (ISFEE)

作者： Michael Schreiber Emil Delic Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specific type of memory, it would be straightforward to determine suitable state-of-the-art tests. However, the question our research focuses on is: “Which RAM tests do not need to be performed due to the safety architecture?” Even high-performance tests do require execution time. In the range of safety-related systems, diagnostics may consume most of the central processing unit (CPU) time, depending on the architecture. Therefore, this paper depicts how architectural characteristics can be taken into account to reasonably simplify specific RAM tests. This paper introduces our research on RAM tests in the range of safety-related systems. Therefore, key topics are introduced, first: comprehensively and starting from scratch, thus enabling anyone to follow our research. Second, an example is shown on how detecting stuck-at faults of address and data words, as demanded by IEC 61508 Ed.2.0, can be simplified by taking advantage of a 1oo2D safety architecture.

关键词： Random access memory Safety IEC standards computer architecture Circuit faults system-on-chip

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Safety chips in light of the standard IEC 61508: Survey and analysis

Safety chips in light of the standard IEC 61508: Survey and ...

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International Symposium on Fundamentals of Electrical Engineering (ISFEE)

作者： A. Hayek J. Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel GERMANY

With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented, which allows the realization and certification of safety-related solutions with on-chip redundancy. In a broader context, the standard ISO 26262 offers similar methodologies for safety solutions for automotive applications. The main focus of the research work of our institute is laid on the development and certification of safety-chips according to the standard IEC 61508. Together with an industrial partner, we are developing chip-based safety-related solutions for several industrial applications. In the same context, several semiconductor manufacturers addressed the development of such solutions in the last years, mainly with the focus on automotive applications. The present paper provides an overview of existing and planned safety chip architectures. Furthermore, a cursory analysis of the presented safety-chips is carried out with respect to the standard IEC 61508. A deep qualitative and quantitative analysis require experiments and simulations which will be carried out in future work.

关键词： Safety IEC standards ISO standards Monitoring computer architecture Software

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Wireless communication modeling for safety related systems

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International Journal of Circuits, systems and Signal Processing 2014年 8卷 330-336页

作者： Pendli, P.K. Schwarz, M. Wacker, H.D. Boercsoek, J. Department of Computer Architecture and System Programming University of Kassel Wilhelmshoeher Allee 71 Kassel34121 Germany

This paper deals with the modeling of wireless communication for safety related systems. To achieve safe wireless communication for safety related systems, the wireless channel is modeled by taking into account both bit errors and erasures (loss of information) that occur during wireless transmission of the information. To reduce the bit errors and to detect the erasures, a coding method for transmitting the code word is suggested in this paper. With this coding method, parameters such as bit error, probability of undetected error are reduced and the bit erasures that occur due to fast fading and channel losses are detected confidently. The safety methods as defined according to the European standard EN 50159-2 are taken into consideration and their implementation to achieve safe wireless communication for safety related systems is explained in this paper. The mathematical derivations to calculate the probability of failures per hour (PFH) values for wireless communication with the suggested coding method are derived. With the derived PFH equation, safety integrity level (SIL) achieved for a particular wireless technology can be determined. Finally, the SIL levels achieved for Bluetooth technology are shown. © 2014 North Atlantic University Union. All rights reserved.

关键词： Bit error rate

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Network-based safety-related vibration and position analysis for railway vehicles

Network-based safety-related vibration and position analysis...

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International Conference on Connected Vehicles and Expo (ICCVE)

作者： Samer Telawi Yusuf Sima Bashier Machmur Ali Hayek Josef Börcsök Udo Pinders Walter Schreiber Department of Computer Architecture and System Programming University of Kassel Kassel Germany Universitat Kassel Kassel Hessen DE Reuschling GmbH & Co KG Hattingen Germany

Nowadays, many considerable efforts are focused on the development of efficient and effective systems that increase the productivity of vehicles by controlling and manipulating the extraordinary states, such as sliding and spinning, during the operational time. Those states play a central role in the performance of the vehicles described as an interaction among different mechanical parts regarding their life-time, their wear and tear, as well as the maintenance costs. In addition, these states ultimately affect the safety of target system and its environment. Therefore, the necessity of avoiding, controlling, or manipulating these states to lower their effects into a tolerable level has become the major driver for conducting the current research work. In this paper, a prototype for safety-related platform for detecting and controlling railway vehicles states by means of vibration capture is presented. Additionally, test procedures in order to collect the vibration data related to each state are presented; these tests were performed under the supervision of an industrial partner. Moreover, the recognized initial patterns of the vibration signals related to the studied states are also introduced.

关键词： Safety Vehicles Acceleration Vibrations computer architecture Sensor systems

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HICore1: “Safety on a chip” turnkey solution for industrial control

HICore1: “Safety on a chip” turnkey solution for industria...

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International Conference on Application Specific systems (ASAP), Architectures and Processors

作者： Ali Hayek Bashier Machmur Michael Schreiber Josef Börcsök Stefan Gölz Mario Epp University of Kassel Chair for Computer Architecture and System Programming Kassel Germany HIMA Paul Hildebrandt GmbH + Co KG Chip-based Solutions Bruhl Germany

In this paper a complete safety controller on a single chip is presented. HICore 1 is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. It also meets the requirements of the standard EN 13849 Performance Level e. A SIL3 operating system and a SIL3 middleware complement the presented safety chip solution. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions ready for certification.

关键词： Safety IEC standards computer architecture Communication systems system-on-chip programming

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V.A. Melnikov - The Architect of Soviet computers and computer systems

V.A. Melnikov - The Architect of Soviet Computers and Comput...

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International Conference on computer Technology in Russia and in the Former Soviet Union (SoRuCom)

作者： Vera Karpova Leonid Karpov S. A. Lebedev Institute of Precise Mechanics and Computer Engineering Russian Academy of Sciences Moscow Russia Institute for System Programming Russian Academy of Sciences Moscow Russia

Member of the Russian Academy of Sciences Vladimir Melnikov was a disciple of the great Russian scientist, academician Sergei Lebedev, who was the founder of the national computer science, the creator of the first Soviet computers, the chief designer of computers that made up the famous BESM line (high-speed electronic computers). Since 1950, being the fifth-year student, he worked in the Academic Institute of Precise Mechanics and computer Engineering (IPMCE), where participated in the development of the first soviet electronic computer. The serial BESM version was called BESM-2, and Melnikov became the executive in charge. Later this computer was replicated in China. A significant role in the life of Melnikov was played by the creation of the transistor BESM-6 computer, on which he worked as a deputy chief designer. In 1967, this computer was put into production and was produced for 17 years. In 1969 Melnikov started the design and development of a computing system "BESM-6 pairing hardware interface" (HI-6). In 1975, during the Soviet-American space flight 'Soyuz-Apollo' the operation was carried out on the system, built on the basis of HI-6 and BESM-6, that also provided a highly automated processing of ballistic and telemetry data in the Soviet Mission Control Center. Since 1978 Melnikov began to develop a new supercomputer, which had the name 'Electronics SS BIS' and was close to the American supercomputer Cray 1 in its instruction set.

关键词： Educational institutions Awards activities Supercomputers computer science Production

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A Tool for reliable model-based design for programming logic controllers

A Tool for reliable model-based design for programming logic...

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1st IFAC Workshop on Advances in Control and Automation Theory for Transportation Applications, ACATTA 2013

作者： Schwarz, M.H. Sheng, H. Chaaban, W. Börcsök, J. Dept. Safety Computer Technology University of Kassel Kassel Germany Dept. Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (纸本)9783902823519

This paper presents an automated code generation and validation, verification approach to convert model based developments into IEC 61131-3 conform function blocks. IEC 61131-3 programming languages are supported by PLC manufacturers and software environment developers and provide the possibility that novel and intelligent algorithms can be directly operated on industrial accepted systems. Railway and transportation also receive drastic changes from purely hardware based systems to microcontroller + software driven systems. However, the conversion has to follow certain steps to ensure that the adaptation is done correctly and functionality is not alternated, added or deleted. Concepts suggested by different international standards such as the IEC 61508 can help to derive a tool chain to verify the generated code. © IFAC.

关键词： Manufacture

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