Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For...
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This paper presents a simulation environment, which is a C++/systemC based integrated framework for functional verification of designed components or electronic architectures and enhances the existing computer archite...
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This paper presents a simulation environment, which is a C++/systemC based integrated framework for functional verification of designed components or electronic architectures and enhances the existing computer architecture simulation tool named sefca. As the VHDL sources are converted to systemC it is sufficient for verification engineers to have a fundamental knowledge of C++ and the systemC library. The testbench framework uses the same graphical user interface (GUI) based on the wxPython library, which was presented in the sefca tool. Verification of the design is supported by the systemC verification library (SCV). Inter-Process-Communication is used to send the stimuli for simulation input from the GUI to the simulation process and the simulation results back to the online viewer in the GUI. With these enhancements sefca becomes a universal tool for testing the software and the hardware part of a new design at the same time. Working on the transaction level model (TLM) the proposed methodology offers a high performance and a high level of abstraction.
Software-Engineering is very important today. In industry (specifically by software critical system) it is important to produce high reliable software, i.e. software with low proportion of faults. To produce such reli...
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Software-Engineering is very important today. In industry (specifically by software critical system) it is important to produce high reliable software, i.e. software with low proportion of faults. To produce such reliable software, a long handling process is required, and because this process consumes a large amount of time and resources to achieve the desired reliability goals it is useful to use Software Reliability Stochastic Models to predict the required software testing time. In this paper a new approach to reflecting the residual number of critical failures in software-systems is introduced. There are currently very few processes enabling us to predict the reliability of the critical failures or the critical failure rate for critical systems. Furthermore, we will focus on distinguishing the critical failures in the software. We will thus distinguish both critical as well as non-critical failures in the Software. Therefore it is important to divide the process into two classes, detection- and correction class. To develop an approach it is necessary to determine corresponding distribution functions and model assumptions.
In the standard IEC 61508 miscellaneous architectures for safety related systems are introduced. Depending on the required safety, reliability and availability levels several architectures such as 1oo2-, 2oo2-, 1oo3-,...
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In the standard IEC 61508 miscellaneous architectures for safety related systems are introduced. Depending on the required safety, reliability and availability levels several architectures such as 1oo2-, 2oo2-, 1oo3-, and 2oo3-architectures can be selected. In this paper, the concept and calculation of a novel architecture is presented. The 1oo4-architecture (one out of four) represents an advanced safety architecture, which is 3-failure safe. This means that at least one of the four channels have to work correctly in order to trigger the safety function. In order to classify the quality of the proposed architecture for safety related systems the PFD-value is calculated. Additionally, the Markov-model for a 1oo4-architecture is introduced and the MTTF-value for this architecture is calculated. The results are high safety and high reliability.
This paper is concerned with the design procedures of an automated testing tool, developed in Matlab ® /Simulink ® environment, that performs software verification during runtime on a PLC (Programmable Logi...
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This paper is concerned with the design procedures of an automated testing tool, developed in Matlab ® /Simulink ® environment, that performs software verification during runtime on a PLC (Programmable Logic Controller) or so called HiL test (Hardware-in-the-Loop) for model-based development of control applications. In addition to checking the “semantic” or “functional” correctness of the automatically generated C++ - Code with RTW (Real Time Workshop ® ) for algorithms designed and developed in Simulink ® on hardware targets, the tool compares results obtained from the HiL test with the results of the MiL test (Model-in-the-Loop) performed in early stage of development for the same developed application. The main purpose behind this work is to develop reliable software that fulfil system requirements and to test its behaviour during realtime hardware simulation, in order to achieve the validation step which represents the terminating - step of almost all projects.
Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For...
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Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime.
This paper introduced the optimization and deoptimization technologies for Escape analysis in open world. These technologies are used in a novel Escape analysis framework that has been implemented in Open runtime plat...
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This paper introduced the optimization and deoptimization technologies for Escape analysis in open world. These technologies are used in a novel Escape analysis framework that has been implemented in Open runtime platform, Intel's opensource Java virtual machine. We introduced the optimization technologies for synchronization removal and object stack allocation, as well as the runtime deoptimization and compensation work. The deoptimization and compensation technologies are crucial for a practical Escape analysis in open world. We evaluated the runtime efficiency of the deoptimization and compensation work on benchmarks like SPECjbb2000 and SPECjvm98.
In chapter 2 the authors firstly give a short outline of Bayesian inference, Bayesian prior and posterior distributions and Bayesian estimators. In chapter 3 they investigate random variables following a Poisson distr...
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ISBN:
(纸本)9784883254194
In chapter 2 the authors firstly give a short outline of Bayesian inference, Bayesian prior and posterior distributions and Bayesian estimators. In chapter 3 they investigate random variables following a Poisson distribution. They then handle the rate parameter as a random variable, and show that the associated posterior distribution is an Erlang distribution. They then calculate the density functions of two ratios related to rate parameters. In chapter 4 the authors are dealing with partial stroke tests, proof tests, failure rates, and diagnostic coverage factors, determine the respective probability density functions and calculate confidence intervals. Finally they discuss the question whether or not to take account of the last failure of a test interval.
The standard IEC/EN 61508 defines the requirements for safety systems to be applied to industrial plant safety independently of the application. It is not only intended as a basis for the development of future applica...
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ISBN:
(纸本)9784883254194
The standard IEC/EN 61508 defines the requirements for safety systems to be applied to industrial plant safety independently of the application. It is not only intended as a basis for the development of future application orientated standards, but also as a basis of all safety related electrical, electronic and programmable electronic systems, in order to apply it to safety critical applications. The purpose of this paper is to describe the SILCas tool which enables the user to determine the Safety Integrity Level (SIL) and the probability of failure on demand (PFD) for entire SIFs (consisting of sensor, signal processing, actuator) and for different system architectures.
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