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作者： Luo, Zhi-Quan Ma, Wing-Kin So, Anthony Ye, Yinyu Zhang, Shuzhong Department of Electrical and Computer Engineering University of Minnesota United States Department of Electronic Engineering Chinese University of Hong Kong Shatin Hong Kong Hong Kong Department of Systems Engineering and Engineering Management Chinese University of Hong Kong Hong Kong Hong Kong Department of Management Science and Engineering MSE Industrial Affiliates Program Stanford University United States

In recent years, the semidefinite relaxation (SDR) technique has been at the center of some of very exciting developments in the area of signal processing and communications, and it has shown great significance and relevance on a variety of applications. Roughly speaking, SDR is a powerful, computationally efficient approximation technique for a host of very difficult optimization problems. In particular, it can be applied to many nonconvex quadratically constrained quadratic programs (QCQPs) in an almost mechanical fashion, including the following problem: © 2010 IEEE.

关键词： Signal processing

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Power efficient voltage islanding for systems-on-chip from a floorplanning perspective 10

Power efficient voltage islanding for Systems-on-chip from a...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Pavel Ghosh Arunabha Sen Computer Science and Engineering Program School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ USA

ISBN: (纸本)9783981080162

Power consumption can be significantly reduced in systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.

关键词： Voltage Energy consumption Cost function Power engineering and energy Minimization Very large scale integration computer science Power engineering computing Informatics systems engineering and theory

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Hardware particle swarm optimization based on the attractive-repulsive scheme for embedded applications

Hardware particle swarm optimization based on the attractive...

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2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010

作者： Muñoz, Daniel M. Llanos, Carlos H. Dos S. Coelho, Leandro Ayala-Rincón, Mauricio Department of Mechanical Engineering Automation and Control Group/GRACO University of Brasilia Brasilia DF Brazil Industrial and Systems Engineering Graduate Program LAS/PPGPES Pontifical Catholic University of Parana Curitiba Parana Brazil Department of Computer Science and Mathematics University of Brasilia Brasilia DF Brazil

ISBN: (纸本)9780769543147

Particle Swarm Optimization (PSO) algorithms have been proposed to solve engineering problems that require to find an optimal point of operation. However, the PSO algorithm suffers from premature convergence and high elapsed time when solving multimodal and large scale engineering problems. This problem becomes an evident drawback for embedded applications in which the microcontrollers often operates at low computational capacity. This paper proposes a hardware implementation of a parallel self-adaptive PSO algorithm based on an attractive-repulsive scheme and using the efficient floating-point arithmetic which performs computations with large dynamic range and high precision. The parallel capabilities of the PSO are exploited by implementing parallel particles directly in hardware in order to decrease the running time. In addition, the attractive-repulsive technique avoids the premature convergence problem by self-adapting the swarm behavior according to its diversity. Synthesis and simulation results for benchmark test problems were performed, demonstrating the correctness of the proposed architectures. Finally, an elapsed time comparison between the hardware and software implementations shows the suitableness of the proposed architecture for embedded applications. © 2010 IEEE.

关键词： Global optimization

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Energy efficient mapping and voltage islanding for regular NoC under design constraints

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International Journal of High Performance systems Architecture 2010年第3-4期2卷 132-144页

作者： Ghosh, Pavel Sen, Arunabha Computer Science Program School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ 85281 United States

Computational energy consumption of the processing elements (PEs) of a NoC can be significantly reduced by scaling down their voltage levels. This creates clusters of adjacent PEs operating at the same voltage level, known as voltage islands. Excessive number of voltage islands is undesirable from the physical design perspective and due to the overhead of level shifter energy consumption between adjacent voltage islands. Considering these issues during mapping of the PEs to the NoC routers, can potentially lead to acceptable solutions with reduced overall energy consumption. In this paper, we formulate the mapping problem as an optimisation problem. We present both optimal solution, obtained by solving a mixed integer linear program (MILP), and heuristic solution based on random greedy selection. Experimental results using benchmark and real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution. Copyright © 2010 Inderscience Enterprises Ltd.

关键词： Network-on-chip

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Understanding transistor channel temperature in nonlinear microwave measurements and device operation

Understanding transistor channel temperature in nonlinear mi...

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ARFTG Conference

作者： Charles Baylis Buford Randall Jean Josh Martin Loria Wang Matthew Moldovan Hunter Miller Wireless and Microwave Circuits and Systems Program Department of Electrical and Computer Engineering Baylor University Waco TX USA

With the widespread use of high-voltage GaN devices and other high-power transistors, understanding the heating of a device during large-signal excitation and measurement is critical, both to ensure efficient operation and to prevent destruction of devices during measurement. Device self-heating during RF excitation is directly dependent upon the power-added efficiency of operation. All DC and RF power that is not converted to output RF power is dissipated in the device as heat. When properly applied, the traditional electrothermal model used in circuit simulators adequately calculates this self heating and yields some interesting results. In this paper, it is demonstrated that the load impedance providing maximum power-added efficiency also results in the lowest average dissipated power, and hence the lowest channel temperature, of the device. The variation in average dissipated power (and hence channel temperature) is also examined for different loading conditions; it is shown that some loading conditions produce a dissipated power that is actually higher than the DC power, a situation which often can lead to device failure during load-pull measurements.

关键词： Radio frequency Power dissipation Temperature measurement Mathematical model Heating Microwave measurements Equations

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LINC power amplifiers for reducing out-of-band spectral re-growth: A comparative study

LINC power amplifiers for reducing out-of-band spectral re-g...

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IEEE Annual Conference on Wireless and Microwave Technology (WAMICON)

作者： Charles Baylis Matthew Moldovan Loria Wang Josh Martin Wireless and Microwave Circuits and Systems Program Department of Electrical and Computer Engineering Baylor University Waco TX USA

ISBN: (纸本)9781424466887;9781424466890

The Linear Amplification with Nonlinear Components (LINC) power amplifier structure combiner implementation has an effect on the linearity and efficiency of the design. Understanding and using this tradeoff is helpful to radar and communication designers and can be used to assist in operating with optimum efficiency while meeting spectral mask requirements instituted by regulatory agencies. In this paper, a simulation-based investigation is performed into implementations with a 180-degree coupler and with a Chireix outphasing network. In general, the overall efficiency in both designs is a function of the amplitude modulation of the message signal in the LINC configuration; however, the 180-degree coupler has a potential to obtain higher linearity in many cases due to the isolation of its two input ports. In certain cases of amplitude modulation, however, much of the output power in the 180-degree coupler design is delivered to an unused termination rather than to the network output.

关键词： Power amplifiers Linearity Amplitude modulation Radar Phase modulation Signal design Voltage Interference Microwave amplifiers Circuits and systems

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Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs

Accelerating the Shuffled Frog Leaping algorithm by parallel...

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2010 IEEE 5th International Conference on Bio-Inspired Computing: Theories and Applications, BIC-TA 2010

作者： Muñoz, Daniel M. Llanos, Carlos H. Dos S. Coelho, Leandro Ayala-Rincón, Mauricio Department of Mechanical Engineering Automation and Control Group/GRACG University of Brasilia Brasilia D.F. Brazil Industrial and Systems Engineering Graduate Program Pontifical Catholic University of Parana Curitiba Parana Brazil Department of Computer Science and Mathematics University of Brasilia Brasilia D.F. Brazil

ISBN: (纸本)9781424464388

Meta-heuristics are efficient techniques for solving large scale optimization problems in which traditional mathematical techniques are impractical or provide sub-optimal solutions. The Shuffled Frog Leaping algorithm (SFLA) is a stochastic iterative method, bio-inspired on the memetic evolution of a group of frogs when seeking for food, which combines the social behavior-based of the particle swarm optimization technique (PSO) and the global information exchange of memetic algorithms. However, the SFLA algorithm suffers on large execution times, being this problem clearly evident when solving complex optimization problems for embedded applications. This drawback can be overcome by exploiting the parallel capabilities of the SFLA. This paper proposes a hardware parallel implementation of the SFLA algorithm (HPSFLA) using FPGAs (Field programmable gate Arrays) and the efficient floating-point arithmetic. The proposed architecture allows the SFLA to improve the functionality of the algorithm as well as to decrease the execution times by implementing parallel frogs and parallel memeplexes. Three well-known benchmark problems have been used to validate the implemented algorithm and simulation results demonstrate that the HPSFLA speeds-up by factors of 362, 727 and 211 a C-code implementation using an embedded microprocessor for the Sphere, Rastrigin and Rosenbrock benchmarks problems, respectively. Synthesis, simulation and execution time results demonstrate the effectiveness of the proposed HPSFLA architecture for embedded optimization systems. © 2010 IEEE.

关键词： Global optimization

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Comparison between two FPGA implementations of the particle swarm optimization algorithm for high-performance embedded applications

Comparison between two FPGA implementations of the particle ...

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2010 IEEE 5th International Conference on Bio-Inspired Computing: Theories and Applications, BIC-TA 2010

作者： Muñoz, Daniel M. Llanos, Carlos H. Dos S. Coelho, Leandro Ayala-Rincón, Mauricio Department of Mechanical Engineering Automation and Control Group/GRACO University of Brasilia Brasilia D.F. Brazil Industrial and Systems Engineering Graduate Program LAS/PPGPES Pontifical Catholic University of Parana Curitiba Parana Brazil Department of Computer Science and Mathematics University of Brasilia Brasilia D.F. Brazil

ISBN: (纸本)9781424464388

Particle Swarm Optimization (PSO) algorithms have been proposed to solve engineering problems that require to find an optimal point of operation. There are several embedded applications which requires to solve online optimization problems with a high performance. However, the PSO suffers on large execution times, and this fact becomes evident when using Reduced Instruction Set computer (RISC) microprocessors in which the operational frequencies are low in comparison with the high operational frequencies of traditional personal computers (PCs). This paper compares two hardware implementations of the parallel PSO algorithm using an efficient floating-point arithmetic which perform computations with large dynamic range and high precision. The full-parallel and the partially-parallel PSO architectures allow the parallel capabilities of the PSO to be exploited in order to decrease the running time. Three well-known benchmark test functions have been used to validate the hardware architectures and a comparison in terms of cost in logic area, quality of the solution and performance is reported. In addition, a comparison of the execution time between the hardware and two C-code software implementations, based on a Intel Core Duo at 1.6GHz and a embedded Microblaze microprocessor at 50MHz, are presented. © 2010 IEEE.

关键词： Global optimization

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Modeling GaN: Powerful but challenging

Modeling GaN: Powerful but challenging

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作者： Dunleavy, Lawrence Baylis, Charles Curtice, Walter Connick, Rick Modelithics Inc. Tampa FL United States Department of Electrical Engineering Center for Wireless and Microwave Information Systems University of South Florida Tampa United States Department of Electrical and Computer Engineering Wireless and Microwave Circuits and Systems Program Baylor University Waco TX United States W.R. Curtice Consulting Washington Crossing PA United States Triquint Semiconductor Apopka FL United States

Gallium nitride transistor-based power amplifiers (PA) which are currently among the most important technologies impacting high-power transmitter design at microwave frequencies are discussed. GaN HEMTs also allow high-power operation at much higher frequencies than silicon laterally diffused metal oxide semiconductor field-effect transistors (LDMOS FETs), currently a staple for the cellular base station industry. The significant attention placed on nonlinear models is in step with the growing community of designers who are using nonlinear circuit simulators with good success to design and optimize high-power amplifiers. The use of pulsed measurements as part of the modeling process, along with sufficiently flexible modeling equations and topologies, is critical for obtaining reliable electrothermal GaN models. The successful modeler will be aware of the need for accurate data, carefully applied extraction methodologies, along with the strengths and limitations of available models to obtain the best results for circuit designers.

关键词： Gallium nitride

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A parallel architecture for Ray-Tracing

A parallel architecture for Ray-Tracing

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IEEE Latin American Symposium on Circuits and systems (LASCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França LAM - Computer Architecture and Microeletronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Department of Electronics Engineering and Telecommunications Universidade do Estado do Rio de Janeiro

Real time rendering of three-dimensional scenes in high photorealistic detail is a hard task, such as in the Ray Tracing rendering algorithm. However, parallel implementations of Ray Tracing have been enabling real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an acceptable performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of Ray Tracing, such as shadows and reflection effects, imposing low area cost and acceptable rendering performance.

关键词： computer architecture Interrupters computers Light sources Process control Real-time systems Telecommunications

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