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Leakage-Aware Modulo Scheduling for Embedded VLIW Processors

Journal of computer Science & Technology 2011年第3期26卷 405-417页

作者：关永薛京灵 College of Information Engineering Capital Normal University Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word （VLIW） architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based （Directed Acyclic Graph） leakage-aware scheduling algorithm.

关键词： leakage power very long instruction word （VLIW） software pipelining modulo scheduling

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Comparison and analyzing propagation models

Comparison and analyzing propagation models

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IEEE Asia-Pacific Conference on Antennas and Propagation (APCAP)

作者： Mehmet Baris Tabakcioglu Doruk Ayberkin Ahmet Cansiz Electricity and Energy Department Bayburt Vocational School of Higher Education Bayburt Turkey Computer Programming Department Bayburt Vocational School of Higher Education Bayburt Turkey Electrical and Electro. Engineering Department Ataturk University Erzurum Turkey

This paper presents a study on a class of algorithms based on Uniform Theory of Diffraction (UTD) for multiple diffractions. S-UTD-CH model can be used for fast and more accurate field prediction for multiple diffractions in transition zone. An extensive simulation results for comparison of UTD based algorithms with respect to the computation time and accuracy was provided.

关键词： Diffraction Accuracy Fresnel reflection Computational modeling Receivers Transmitters Antennas

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Quantifying the necrotic areas on liver tissues using support vector machine (SVM) algorithm and Gabor filters

Quantifying the necrotic areas on liver tissues using suppor...

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IEEE International Symposium on Innovations in Intelligent Systems and Applications (INISTA)

作者： Turgut Özseven Metin Ertürkler Mustafa Nurmuhammed Mehmet Gül Murat Harputluoğlu Department of Computer Programming Turhal Vocational School Gaziosmanpaşa University Tokat Turkey Department of Computer Engineering Engineerinig Faculty İnönü University Malatya Turkey Department of Histology and Embryology Faculty of Medicine İnönü University Malatya Turkey Department of Internal Diseases Faculty of Medicine İnönü University Malatya Turkey

Liver is a vital organ of a body that has numerous functions. Severe malfunctioning of these functions causes a liver necrosis. The diagnosis of this necrosis is performed by a specialist who uses appropriate microscopic analysis. However, because this analysis is based on specialist's opinion, the results could be subjective and error prone. The aim of this study is to quantify the hepatic necrotic areas using computer aided algorithms and provide quantitative results that are not prone to errors.

关键词： Gabor filters Liver Support vector machines Feature extraction Training Design automation Educational institutions

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Evaluations of Different Simultaneous Localization and Mapping (SLAM) Algorithms

Evaluations of Different Simultaneous Localization and Mappi...

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Annual Conference on IEEE Industrial Electronics Society

作者： Gurkan Tuna Kayhan Gulez V. Cagri Gungor T. Veli Mumcu Trakya University Department of Computer Programming Yildiz Technical University Electrical-Electronics Faculty Control and Automation Eng. Dept. Bahcesehir University Faculty of Engineering Department of Computer Engineering

ISBN: (纸本)9781467324199

Simultaneous Localization and Mapping (SLAM) algorithms with multiple autonomous robots have received considerable attention in recent years. In general, SLAM algorithms use odometry information and measurements from exteroceptive sensors of robots. The accuracy of these measurements and the performance of the corresponding SLAM algorithm directly affect the overall success of the system. This paper presents comparative performance evaluations of three Simultaneous Localization and Mapping (SLAM) algorithms using Extended Kalman Filter (EKF), Compressed Extended Kalman Filter (CEKF) and Unscented Kalman Filter (UKF). Specifically, it focuses on their SLAM performances and processing time requirements. To show the effect of CPU power on the processing time of SLAM algorithms, two notebooks and a netbook with different specifications have been used. Comparative simulation results show that processing time requirements are consistent with the computational complexities of SLAM algorithms. The results we obtained are consistent with the CPU power tests of independent organizations and show that higher processing power decreases processing time accordingly. The results also show that CEKF is more suitable for outdoor SLAM applications where there are a lot of natural and artificial features.

关键词： Simultaneous localization and mapping Navigation Visualization Power measurement Estimation MONOS devices

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The Relationship between Diagnostic Coverage and Proof Test Interval for 1oo2 and 1oo2D Architectures

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IFAC Proceedings Volumes 2012年第24期45卷 181-184页

作者： İlker üstoğlu özgür T. Kaymakçı Josef Börcsök Yıldız Technical University Davutpaşa Campus A209 34220 34220 Esenler İstanbul TURKEY (Tel: +90-535-418-22-64 ) Yıldız Technical University Davutpaşa Campus A210 34220 34220 Esenler İstanbul TURKEY University Kassel Faculty of Electrical Engineering/Computer Science Department of Computer Architecture and System Programming Wilhelmshöher Allee 71 34121 Kassel GERMANY

In order to measure the effectiveness of safety protection systems there are several design parameters. Diagnostic coverage factor is one of the most important parameter which influences all architectures. In this short paper the relationship between PFD avg , DC and T I are presented. 1oo2 and 1oo2D architectures are considered as examples.

关键词： Functional safety 1002 architecture

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Editorial: Special issue dedicated to ICFP 2010

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Journal of Functional programming 2012年第4-5期22卷 379-381页

作者： UMUT A. ACAR JAMES CHENEY STEPHANIE WEIRICH Programming Languages and Systems Group Max Planck Institute for Software Systems Germany (e-mail: umut@***) Laboratory for Foundations of Computer Science University of Edinburgh Edinburgh UK (e-mail: jcheney@inf.ed.ac.uk) School of Engineering and Applied Science University of Pennsylvania Philadelphia PA 19104 USA (e-mail: sweirich@cis.upenn.edu)

The 15th ACM SIGPLAN International Conference on Functional programming (ICFP) took place on September 27–29, 2010 in Baltimore, Maryland. After the conference, the programme committee, chaired by Stephanie Weirich, selected several outstanding papers and invited their authors to submit to this special issue of Journal of Functional programming. Umut A. Acar and James Cheney acted as editors for these submissions. This issue includes the seven accepted papers, each of which provides substantial new material beyond the original conference version. The selected papers reflect a consensus by the program committee that ICFP 2010 had a number of strong papers that link core functional programming ideas with other areas, such as multicore, embedded systems, and data compression.

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SFMalloc: A lock-free and mostly synchronization-free dynamic memory allocator for manycores

SFMalloc: A lock-free and mostly synchronization-free dynami...

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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Seo, Sangmin Kim, Junghyun Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9780769545660

As parallel programming becomes the mainstream due to multicore processors, dynamic memory allocators used in C and C++ can suppress the performance of multi-threaded applications if they are not scalable. In this paper, we present a new dynamic memory allocator for multi-threaded applications. The allocator never uses any synchronization for common cases. It uses only lock-free synchronization mechanisms for uncommon cases. Each thread owns a private heap and handles memory requests on the heap. Our allocator is completely synchronization-free when a thread allocates a memory block and deallocates it by itself. Synchronization-free means that threads do not communicate with each other at all. On the other hand, if a thread allocates a block and another thread frees it, we use a lock-free stack to atomically add it to the owner thread's heap to avoid the memory blowup problem. Furthermore, our allocator exploits various memory block caching mechanisms to reduce the latency of memory management. Freed blocks or intermediate memory chunks are cached hierarchically in each thread's heap and they are used for future memory allocation. We compare the performance and scalability of our allocator to those of well-known existing multi-threaded memory allocators using eight benchmarks. Experimental results on a 48-core AMD system show that our approach achieves better performance than other allocators for all benchmarks and is highly scalable with a large number of threads. © 2011 IEEE.

关键词： Synchronization

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A software-managed coherent memory architecture for manycores

A software-managed coherent memory architecture for manycore...

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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Park, Jungho Jang, Choonki Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9780769545660

Cache coherent Non-Uniform Memory Access (cc-NUMA) architectures have been widely used for chip multiprocessors (CMPs). However, they require complicated hardware to properly handle the cache coherence problem. Moreover, it generates heavy on-chip network traffic due to the coherence enforcement. In this work, we propose a simple software-managed coherent memory architecture for manycores. Our memory architecture exploits explicitly addressed local stores. Instead of implementing the complicated cache coherence protocol in hardware, coherence and consistency are supported by software, such as a runtime or an operating system. The local stores together with the software leverage conventional caches to make the architecture much simpler and to generate much less network traffic than conventional ccNUMA-based CMPs. Experimental results indicate that our approach is promising. © 2011 IEEE.

关键词： Memory architecture

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An OpenCL framework for homogeneous manycores with no hardware cache coherence

An OpenCL framework for homogeneous manycores with no hardwa...

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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Lee, Jun Kim, Jungwon Kim, Junghyun Seo, Sangmin Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9780769545660

Recently, Intel has introduced a research prototype manycore processor called the Single-chip Cloud computer (SCC). The SCC is an experimental processor created by Intel Labs. It contains 48 cores in a single chip and each core has its own L1 and L2 caches without any hardware support for cache coherence. It allows maximum 64GB size of external memory that can be accessed by all cores and each core dynamically maps the external memory into their own address space. In this paper, we introduce the design and implementation of an OpenCL framework (i.e., runtime and compiler) for such manycore architectures with no hardware cache coherence. We have found that the OpenCL coherence and consistency model fits well with the SCC architecture. The OpenCL's weak memory consistency model requires relatively small amount of messages and coherence actions to guarantee coherence and consistency between the memory blocks in the SCC. The dynamic memory mapping mechanism enables our framework to preserve the semantics of the buffer object operations in OpenCL with a small *** have implemented the proposed OpenCL runtime and compiler and evaluate their performance on the SCC with OpenCL applications. © 2011 IEEE.

关键词： Semantics

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Data transmission via erasure type channels protected by linear codes

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Journal of Physics: Conference Series 2012年第1期364卷

作者： H D Wacker P Pendli J Börcsök To whom any correspondence should be addressed University Kassel Faculty of Electrical Engineering/Computer Science Department of Computer Architecture and System Programming Wilhelmshöher Allee 71 34121 Kassel

The paper is concerned with data transmission via channels composed of a memoryless binary symmetric channel and the erasure channel of Peter Elias. Channels of this type play an important role in modelling different types of networks especially wireless networks, and have been investigated using, amongst others, the theory of Markov chains. Channel Capacities and network flows have been determined. The authors focus their interest on some aspects of coding theory. They assume the data transmission to be protected by a linear code, a CRC for example, and determine the probability of undetected error of the code. They then consider redundant transmission via two or more channels with bit inversion, and calculate the probability of undetected error. They prove some inequalities that are useful instruments to estimate the rate of transmission errors and to determine safety integrity levels according to the standards. Finally the authors apply their results to Bluetooth channels suffering from different types of noise.

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