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Annual Symposium on Simulation

作者： M.Y.H. Low Programming Research Group Computing Laboratory University of Oxford Oxford UK

The performance of a parallel simulation system depends very much on partitioning simulation workload evenly among the set of processors in the computing environment to ensure load-balance between processors. Most parallel simulation systems employ user-defined static partitioning. However static partitioning requires in-depth domain knowledge of the specific simulation model in the study. It is not effective if the workload of a simulation model could not be quantified accurately or changes over time during a simulation run. Dynamic load-balancing allows the simulation system to automatically balance the workload of different simulation models without user's input. In this paper the use of dynamic load-balancing in the context of the BSP Time Warp optimistic protocol is examined. Based on the BSP cost model, a dynamic load-balancing algorithm for the BSP Time Warp protocol is developed. Using different simulation models, the paper shows that to achieve consistent performance, the dynamic load-balancing algorithm for BSP Time Warp needs to consider both computation and communication workload, as well as lookaheads between processors.

关键词： Computational modeling Costs Protocols Concurrent computing Heuristic algorithms Time warp simulation Computational efficiency Algorithm design and analysis Parallel programming Load modeling

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Consistent modeling of distributed mutual exclusion protocol using optimistic simulation 01

Consistent modeling of distributed mutual exclusion protocol...

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Proceedings of the fifteenth workshop on Parallel and distributed simulation

作者： Malcolm Yoke Hean Low David M. Nicol Programming Research Group Computing Laboratory University of Oxford Dept. of Computer Science Dartmouth College

ISBN: (纸本)9780769511047

This paper discusses the problem of risk in optimistic simulation protocols, using as example simulation of a distributed mutual exclusion protocol with strong consistency properties. The simulation model is augmented to detect model inconsistency errors resulting from risky optimistic simulation. While the model runs sequentially without consistency errors, errors occur when the model is executed in parallel optimistically. Some of the errors entirely violate the fundamental mutual exclusion properties of the model itself. To address this problem we extend the optimistic simulation library to eliminate these inconsistencies. We discuss the details of these extensions and the performance trade-off for adding them.

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Consistent modeling of distributed mutual exclusion protocol using optimistic simulation

Consistent modeling of distributed mutual exclusion protocol...

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Workshop on Principles of Advanced and Distributed Simulation (PADS)

作者： M.Y.H. Low D.M. Nicol Programming Research Group Computing Laboratory University of Oxford UK Department of Computer Science Dartmouth College USA

ISBN: (纸本)076951104X

This paper discusses the problem of risk in optimistic simulation protocols, using as an example, simulation of a distributed mutual exclusion protocol with strong consistency properties. The simulation model is augmented to detect model inconsistency errors resulting from risky optimistic simulation. While the model runs sequentially without consistency errors, errors occur when the model is executed in parallel optimistically. Some of the errors entirely violate the fundamental mutual exclusion properties of the model itself. To address this problem, we extend the optimistic simulation library to eliminate these inconsistencies. We discuss the details of these extensions and the performance tradeoff for adding them.

关键词： Protocols Computational modeling Libraries Hazards Computer simulation Laboratories Computer science Educational institutions Computer errors Parallel processing

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Weakest specifunctions for BSP

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Parallel Processing Letters 2001年第4期11卷 439-454页

作者： Chen, Yifeng Sanders, J.W. Department of Maths and Computer Science University of Leicester University Road Leicester LE1 7RH United Kingdom Programming Research Group Oxford University Computing Laboratory Parks Road Oxford OX1 3QD United Kingdom

This paper introduces a calculus of weakest specification for supporting reuse of established components in deriving a design (in the sense of formal methods). The weakest specifunction generalizes the notions of weakest pre-specification and weakest parallel environment;but instead of calculating the weakest required component of a target specification, it calculates the weakest specification function whose value refines the target when applied to an established component. In particular it overcomes the restriction of those other calculi to taking merely one required component at a time. The theory of specifunctions is applied to a new weakest-design calculus in the context of BSP. The calculus is based on the par-seq specifunction which involves two required components: it places one established component in parallel with one required component and the result in sequence with another required component to meet a given specification. A calculus is provided for the par-seq specifunction and it is applied to the derivation of a distributed BSP algorithm for greatest common divisor.

关键词： Parallel processing systems

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Unifying theories of healthiness condition

Unifying theories of healthiness condition

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Asia-Pacific Conference on Software Engineering

作者： He Jifeng C.A.R. Hoare International Institute for Software Technology United Nations University Macau Macao China Computing Laboratory Programming Research Group Oxford University Oxford UK

A theory of programming starts with a complete Boolean algebra of specifications, and defines healthiness conditions which exclude infeasibility of implementation. These are expressed as algebraic laws useful for transformation and optimisation of designs. programming notations and languages must be restricted to those preserving all the healthiness conditions. We have explored a wide range of programming paradigms, including nondeterministic, sequential, parallel, logical and probabilistic. In all cases, we have found a single healthiness condition, formalised by constructions due to Karoubi and to Kleisli. The uniformity maintains for all paradigms a single notion of correctness throughout the chain that leads from specification through designs to programs that are proved to meet the original specification.

关键词： Design optimization Laboratories Boolean algebra Logic programming Parallel programming Maintenance Specification languages

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Implementation lessons of performance prediction tool for parallel conservative simulation 6

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6th International European Conference on Parallel computing, Euro-Par 2000

作者： Lim, Chu-Cheow Low, Yoke-Hean Gan, Boon-Ping Cai, Wentong Intel Corporation SC12-305 2000 Mission College Blvd Santa ClaraCA95052-8119 United States Programming Research Group Oxford University Computing Laboratory University of Oxford OxfordOX1 3QD United Kingdom Gintic Institute of Manufacturing Technology 71 Nanyang Drive Singapore638075 Singapore Center for Advanced Information Systems School of Applied Science Nanyang Technological University Singapore639798 Singapore

ISBN: (纸本)9783540679561

Performance prediction is useful in helping parallel programmers answer questions such as speedup scalability. Performance prediction for parallel simulation requires first working out the performance analyzer algorithms for specific simulation protocols. In order for the prediction results to be close to the results from actual parallel executions, there are further considerations when implementing the analyzer. These include (a) equivalence of code between the sequential program and parallel program, and (b) system effects (e.g. cache miss rates and synchronization overheads in an actual parallel execution). This paper describes our investigations into these issues on a performance analyzer for a conservative, "super-step" (synchronous) simulation protocol. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Forecasting

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PRAM programming: in theory and in practice

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Concurrency and Computation: Practice and Experience 2000年第4期12卷

作者： D. S. Lecomber C. J. Siniolakis K. R. Sujithan Programming Research Group Oxford University Computing Laboratory Oxford OX1 3QD U.K.

That the influence of the PRAM model is ubiquitous in parallel algorithm design is as clear as the fact that it is technologically infeasible for the forseeable future. The current generation of parallel hardware prominently features distributed memory and high-performance interconnection networks—very much the antithesis of the shared memory required for the PRAM model. It has been shown that, in spite of communication costs, for some problems very fast parallel algorithms are available for distributed-memory machines—from embarassingly parallel problems to sorting and numerical analysis. In contrast it is known that for other classes of problem PRAM-style shared-memory simulation on a distributed-memory machine can, in theory, produce solutions of comparable performance to the best possible for such architectures. The Bulk Synchronous Parallel (BSP) model accurately represents most parallel machines—theoretical and actual—in an execution and cost model. We introduce a scalable portable PRAM realization appropriate for BSP computers and a methodology for usage. Our system is fast and built upon the familiar sequential C++ coupled with the new standard BSP library of parallel computation and communication primitives. It is portable to and predictable on a vast number of parallel computers including workstation clusters, a 256-processor Cray T3D, an 8-node IBM SP/2 and a 4-node shared-memory SGI Power Challenge machine. Our approach achieves simplicity of programming over direct-mode BSP programming for reasonable overhead cost. We objectively compare optimized BSP and PRAM algorithms implemented with our C++ PRAM library and provide encouraging experimental results for our new style of programming. Copyright © 2000 John Wiley & Sons, Ltd.

关键词： PRAM latency hiding BSP distributed memory simulation parallel algorithms

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A framework for model-checking timed CSP

A framework for model-checking timed CSP

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作者： Ouaknine, Joël Programming Research Group Oxford Univ. Computing Laboratory

A framework for model-checking timed CSP processes within a new model of standard CSP was discussed. The timing of events was provided by the consistent and regular communication of a special tock event, analogous to the tick of a clock. A translation function TCSP&rarrCSP was done inductively over syntax of TCSP processes to equate every elapsed time unit with the communication of k tocks. It was observed that event occurance and timeout did not lead to an accumulation of timing errors.

关键词： Real time systems

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A framework for model-checking timed CSP

A framework for model-checking timed CSP

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IEE Colloquium on Applicable Modelling, Verification and Analysis Techniques for Real-Time Systems (Ref. No. 1999/006)

作者： J. Ouaknine Programming Research Group Oxford University Computing Laboratory UK

Timed CSP is a well-known process algebra, built as an extension to Hoare's original CSP, designed to handle concurrency combined with timing considerations. It achieves this over a continuous time domain (the non-negative real numbers), which has the drawback of precluding standard model-checking approaches, as the state-space of any process is naturally a priori (uncountably) infinite. This paper shows how to circumvent this problem by translating and reinterpreting timed CSP processes within a new model of standard CSP. In this discrete model, which draws on previous work by A.W. Roscoe (1997) and A. Mukkaram (1993), timing of events is provided by the consistent and regular communication of a special tock event, analogous to the 'tick' of a clock. The various parallel components of a process are therefore required to synchronise on tock, ensuring a uniform rate of passage of time. General results yielding tight bounds on the loss of information inherent to the translation are given.

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Hardware/software codesign for FPGA-based systems

Hardware/software codesign for FPGA-based systems

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： J.M. Saul Computing Laboratory Programming Research Group Oxford University Oxford UK

A new codesign compiler called Dash (Design Automation for Software and Hardware) provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrised. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

关键词： Hardware Field programmable gate arrays Software systems Computer architecture Design automation Application software Software tools Acceleration Laboratories Hip

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