Three-dimensional (3D) representation of cultural heritage in a digital environment is coming into prominence for documentation of geometric and semantic details and the interpretation of shape representation from aca...
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One of the new tools included in the AV1 video codec is the adaptive filtering scheme used in the sample interpolation process. This scheme includes three different filter families called Regular, Sharp and Smooth, of...
One of the new tools included in the AV1 video codec is the adaptive filtering scheme used in the sample interpolation process. This scheme includes three different filter families called Regular, Sharp and Smooth, offering high flexibility for motion estimation (ME) and motion compensation (MC). However, the high number of interpolation filters also leads to greater complexity and energy consumption, since the generation of samples at sub-pixel position is a costly process. This paper proposes a low-power and high-throughput hardware accelerator focused on the AV1 interpolation filters called Multiversion Interpolation Processor (MVIP). The accelerator includes the three AV1 interpolation filter families, with versions that employ operand isolation for power reduction in unused filters. The accelerator also includes a precise MVIP assuming the MC scenario, besides two approximate versions to reduce the cost on the ME scenario. The proposed design is able to process 8K video at 50fps in MC and 2,656.14 Msamples/sec in ME, with a power dissipation of 41.30mW.
Adaptive filtering plays an essential role in digital signal processing (DSP), being present in many application fields such as noise reduction, telecommunication, and audio signal processing. Notably, the least mean ...
Adaptive filtering plays an essential role in digital signal processing (DSP), being present in many application fields such as noise reduction, telecommunication, and audio signal processing. Notably, the least mean square (LMS) and its normalized version (NLMS) are the most used algorithms due to their simplicity and robustness, which turn them attractive to hardware solutions. This work proposes architectural solutions for LMS and NLMS algorithms targeting an energy-efficient VLSI design. We explore fully sequential, fully parallel, and semi-parallel architectures reusing the hardware as much as possible for both algorithms. It allows for investigating the number of steps necessary for each architecture, demonstrating the energy per operation, circuit area, and throughput savings. The synthesis results highlight the semi-parallel architectures LMS-2 steps and NLMS-3 steps have the best trade-off energy-speed. In addition, we proved the architecture’s energy efficiency in a harmonic canceling case study, achieving more than 60% in energy savings using both filters.
Deep learning has been a popular topic and has achieved success in many areas. It has drawn the attention of researchers and machine learning practitioners alike, with developed models deployed to a variety of setting...
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In the context of optimizing herd management and animal health monitoring, this study aims to enhance the understanding of livestock feeding behavior through precise monitoring of the time each animal spends at the tr...
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ISBN:
(数字)9798350350708
ISBN:
(纸本)9798350350715
In the context of optimizing herd management and animal health monitoring, this study aims to enhance the understanding of livestock feeding behavior through precise monitoring of the time each animal spends at the trough. The primary objective is to optimize feed supply management while concurrently enabling early detection of potential health issues. The fundamental innovation of this study revolves around the creation of an Internet of Things (IoT) Platform, leveraging Ultra High Frequency (UHF) Radio-Frequency Identification (RFID) tags and a specialized antenna cable. This platform facilitates the meticulous recording of animals' ingress and egress times at the feeding trough, thereby providing valuable insights for improved livestock management and health monitoring.
Penile cancer, although rare, has an increasing mortality rate in Brazil, highlighting the need for effective diagnostic methods. Artificial Intelligence (AI) in histopathological analysis can speed up and objectify d...
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Penile cancer, although rare, has an increasing mortality rate in Brazil, highlighting the need for effective diagnostic methods. Artificial Intelligence (AI) in histopathological analysis can speed up and objectify diagnosis, but designing an ideal architecture is challenging. In this study, we propose a neural architecture search (NAS) methodology for detecting penile cancer in digital histopathology images. We explored different configurations of stem blocks and the inclusion of attention mechanisms, highlighting specific preferences depending on the magnification of the images. The results showed that the NAS methodology enabled the discovery of more accurate and optimized architectures for this task, surpassing conventional models. The proposed models achieve 89.5% and 88.5% F1-Score for 40X and 100X magnification, respectively.
Overconsumption of resources is a global issue. To deal with resource depletion and mitigate impending crises, the circular economy (CE) solution provides an ecosystem by reducing waste via the reuse, repair, refurbis...
Overconsumption of resources is a global issue. To deal with resource depletion and mitigate impending crises, the circular economy (CE) solution provides an ecosystem by reducing waste via the reuse, repair, refurbishment, and recycling the existing materials and products. However, as the complexity of supply chains is increasing an effective CE management is very crucial. We want to address this issue by performing a feasibility study with AI-enabled blockchain technology using our developed customised NFT platform, TrackGenesis NFT, along with the *** architecture for CE management to decrease transaction costs, enhance performance and communication along the supply chain, and reduce carbon footprints. Circulogy is an e-waste management system that can respond to supply chain challenges using blockchain technologies. A supply chain can get complicated very quickly, considering that each product component has its supply chain. In our proposed solution, blockchain provides a solution to this by establishing transparency in every node of the product's lifecycle and users can exchange or sell/buy NFTs. There are multiple copies of the audit trail for every transaction using blockchain, which will provide the ability to track and reuse/recycle Waste Electric and Electronic Equipment (WEEE).
Diabetic Retinopathy is one of the main causes of vision loss and can be identified through ophthalmological exams that aim to locate the presence of retinal lesions such as microaneurysms, hemorrhages, soft exudates,...
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Diabetes mellitus is one of the most pressing health concerns because so many people are afflicted by its disabling symptoms. Factors such as age, excess body fat, insufficient physical activity, a history of diabetes...
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Thanks to the high energy efficiency achieved by approximate circuits, the exploration of approximate solutions for a wide of applications is the focus of academic and industrial research. However, defining the most a...
Thanks to the high energy efficiency achieved by approximate circuits, the exploration of approximate solutions for a wide of applications is the focus of academic and industrial research. However, defining the most appropriate approximation considering the power consumption and accuracy trade-off can be exhaustive. This paper proposes a novel approach to estimate the synthesis results for approximate adders (AxA) with different bit-width and approximation levels based on a database and simple mathematical operations to reduce the synthesis process complexity during an approximate circuit development. We implement the proposed approach to estimate the synthesis results for the Copy, Error-Tolerant Adder I (ETA-I), Lower-part-or (LOA), and Truncation (Trunc) AxAs. Comparing our estimation with real synthesis results obtained by an industrial synthesis tool, we prove the approach’s efficiency by presenting an average error on the estimated parameters (area, power and delay) less than 10% in the worst case. In addition, our approach reduces by more than 25 times the number of synthesis runs when estimating the synthesis results for all circuits in the bit width range of 2 to 64 with all possible approximation levels.
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