In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. T...
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Large cities situated within the developing countries facing one of the most important problems are heavy traffic congestion. It happened because of fast urbanization n. Many modern infrastructures for constructing a ...
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While many studies have shown that auditory and visual information influence each other, the link between some intermodal associations are less clear. We here replicate and extend an earlier experiment with ratings of...
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We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and...
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We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and the random dopant fluctuation (RDF) of CFETs are statistically estimated using an experimentally validated device simulation technique. Among five factors of PVE, the channel thickness (T Nch /T Pch ), the channel width (W ch ), and the gate length (L G ) are significant. Owing to superior GAA channel control and increased effective gate area, both WKF and RDF are suppressed. Notably, the PVE on both N-/P-FETs of GAA Si CFET induce the largest off-state current fluctuations of 80% and 278%, respectively, because the device characteristic is very sensitive to the layer thickness and width of channel.
The decision tree ensembles use a single data feature at each node for splitting the data. However, splitting in this manner may fail to capture the geometric properties of the data. Thus, oblique decision trees gener...
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Simulations and diagnostics of high-energy-density plasmas and warm dense matter rely on models of material response properties, both static and dynamic (frequency-dependent). Here, we systematically investigate varia...
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We report for the first time a novel structure of tunneling field-effect transistors (TFETs) with ferroelectric and nanowire concepts. The device is modeled carefully to utilize the benefits of ferroelectrics through ...
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We report for the first time a novel structure of tunneling field-effect transistors (TFETs) with ferroelectric and nanowire concepts. The device is modeled carefully to utilize the benefits of ferroelectrics through metal-ferroelectric by enhancing the internal voltage across the ferroelectric region. The physical behavior of proposed design is analyzed for the improvement of device performance in comparison to the nominal ferroelectric-insulator TFET structure. The proposed design is capable in delivering impressive figures in Ion as 212 μA/μm. reasonable Ioff together with steep subthreshold swing of 33.3 mV/dec.
Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- effic...
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ISBN:
(数字)9781728180588
ISBN:
(纸本)9781728180595
Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.
Fifth-generation (5G) networks enable a variety of use cases, e.g., Ultra-Reliable and Low-Latency Communications, enhanced Mobile Broadband, and massive Machine Type Communication. To explore the full potential of th...
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