Clouds LISP distributed environments (CLIDE) is a distributed, persistent object-based symbolic programming system being implemented on the Clouds distributed operating system. LISP environment instances are stored as...
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Clouds LISP distributed environments (CLIDE) is a distributed, persistent object-based symbolic programming system being implemented on the Clouds distributed operating system. LISP environment instances are stored as large-grained persistent objects, enabling users on many machines to share the contents of these environments through interenvironment evaluations. CLIDE provides a comprehensive research environment for distributed symbolic language, invocation and consistency semantics, and an implementation vehicle for the construction of the symbolic processing portions of complex megaprogrammed systems.< >
A lossless data compression scheme is investigated with a view to improving the compression ratio for practical use. A new scheme called multidictionary compression is proposed which uses a local dictionary and a glob...
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A lossless data compression scheme is investigated with a view to improving the compression ratio for practical use. A new scheme called multidictionary compression is proposed which uses a local dictionary and a global dictionary for removing local and global redundance respectively. An implementation method for this scheme is also provided. Based on the scheme and the implementation method, a compression program called zaa has been implemented. Many experiments with zaa and other compression programs, using several kinds of data, show that the compression ratio of zaa is generally better than those of the other programs.< >
A scheme is developed for providing predictable interprocess communication in real-time systems with (partially connected) point-to-point interconnection networks, which provides guarantees on the maximum delivery tim...
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A scheme is developed for providing predictable interprocess communication in real-time systems with (partially connected) point-to-point interconnection networks, which provides guarantees on the maximum delivery time for messages. This scheme is based on the concept of a real-time channel, a unidirectional connection between source and destination. A real-time channel has parameters which describe the performance requirements of the source-destination communication, e.g., from a sensor station to a control site. Methods to compute guarantees for the delivery time of messages belonging to real-time channels are examined. Problems associated with allocating buffers for these messages are addressed, and a scheme which preserves delivery time guarantees is developed.< >
In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is ...
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In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. In the present work, the authors consider the problem of yield enhancement along the same lines as above not only for PGAs but also for wafer-scale-integrated arrays. A heuristic algorithm for reconfiguration based on a graph-theoretic formulation of the problem and a polynomial-time exact algorithm for a special case of the problem are presented. The reconfiguration algorithms are evaluated by comparing the routability and wire length of the reconfigured and initial placements of the circuit.< >
We present an overview, mainly of work in our laboratory, of low-threshold GaAs/AlGaAs quantum-well laser diodes and GaAs metal-semiconductor-metal photodetectors—two optoelectronic devices which show good ...
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We present an overview, mainly of work in our laboratory, of low-threshold GaAs/AlGaAs quantum-well laser diodes and GaAs metal-semiconductor-metal photodetectors—two optoelectronic devices which show good promise for use in computer-related communication. Present-day telecommunication device technology (based on InP materials) is not well suited to the requirements of optical data communication among and within computers because the computer environment is much more demanding. It imposes a higher ambient temperature on the devices, and requires denser packaging and smaller power dissipation per device, as well as a high degree of parallelism. The GaAs/AlGaAs device technology is ideally suited to this task because of the possibility of integration of arrays of high-speed, low-threshold laser diodes and high-speed photodetectors with high-performance electronic circuits.
It is well known that reducing gate length is a powerful means to increase the transconductance and transit frequency of GaAs MESFET devices. However, by reducing the gate length without scaling channel doping and thi...
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It is well known that reducing gate length is a powerful means to increase the transconductance and transit frequency of GaAs MESFET devices. However, by reducing the gate length without scaling channel doping and thickness, the performance obtained is limited by short-channel effects and parasitics. In this paper we present an overview of our work on two different MESFET structures, illustrating how device performance can be increased by decreasing the gate length, with the result that appropriately scaled MESFETs compare favorably with GaAs-AlGaAs heterojunction FETs. From our work—including some recent results on 0.15-µm-gate-length implantation-self-aligned MESFETs—we conclude that it should be possible to increase the speed of high-speed GaAs MESFET (logic, analog, and microwave) circuits through the use of devices having gate lengths less than 0.5 µm.
作者：
DAHL, VPOPOWICH, F1. School of Computing Science
Centre for Systems Science Laboratory for Computer and Communications Research Simon Fraser University V5A 1S6 Burnaby British Columbia Canada
Static Discontinuity Grammar (SDG) is a type of logic grammar. Its distinctive features are that rules can state dependencies between any two or more subtrees in a derivation tree for a grammatical sentence, and that ...
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Static Discontinuity Grammar (SDG) is a type of logic grammar. Its distinctive features are that rules can state dependencies between any two or more subtrees in a derivation tree for a grammatical sentence, and that descriptions are expressed in terms of node domination in the tree. In this paper, we look at different ways of processing SDGs. The parsing methods of top-down depth-first, and left-corner interpreters are examined for SDGs, as well as a compiler that generates code for both analysis and synthesis. We then introduce some examples and use them to compare the efficiency of our different processing methods. We also discuss related work, including the SDG formalism vs. other logic grammar formalisms.
We discuss methods for solving medium to large-scale sparse least-squares problems on supercomputers, illustrating our remarks by experiments on the CRAY-2 supercomputer at Harwell. The method we are primarily concern...
A methodology for automatically synthesizing a testable RTL (register-transfer-level) hardware specification from a behavioral VHDL (VHSIC hardware description language) specification is presented. Behavioral synthesi...
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A methodology for automatically synthesizing a testable RTL (register-transfer-level) hardware specification from a behavioral VHDL (VHSIC hardware description language) specification is presented. Behavioral synthesis is described. It consists of the automatic creation of a hardware specification, given an input specification that describes how the hardware operates in response to its current state and the states of its input signals. The synthesis methodology includes techniques for ensuring that the resulting hardware is testable. The techniques used for mapping the input behavioral model to hardware assume that the resulting hardware is fully synchronous and serial scan compatible. The synthesis process recognizes expressions and operations in the behavioral model and maps them to corresponding hardware components that are included in a separate VHDL library.< >
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