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2020 IEEE Power and Energy Society General Meeting, PESGM 2020

作者： Xu, Yijun Karra, Kiran Mili, Lamine Korkali, Mert Chen, Xiao Hu, Zhixiong Virginia Tech Northern Virginia Center Bradley Department of Electrical and Computer Engineering Falls ChurchVA22043 United States Johns Hopkins University Applied Physics Lab BaltimoreMD21218 United States Lawrence Livermore National Laboratory Computational Engineering Division LivermoreCA94550 United States Center for Applied Scientific Computing Lawrence Livermore National Laboratory LivermoreCA94550 United States University of California-Santa Cruz Department of Statistics Santa CruzCA95064 United States

ISBN: (纸本)9781728155081

The increasing penetration of renewable energy along with the variations of the loads bring large uncertainties in the power system states that are threatening the security of power system planning and operation. Facing these challenges, this paper proposes a cost-effective, nonparametric method to quantity the impact of uncertain power injections on the load margins. First, we propose to generate system uncertain inputs via a novel vine copula due to its capability in simulating complex multivariate highly dependent model inputs. Furthermore, to reduce the prohibitive computational time required in the traditional Monte-Carlo method, we propose to use a nonparametric, Gaussian-process-emulator-based reduced-order model to replace the original complicated continuation power-flow model. This emulator allows us to execute the time-consuming continuation power-flow solver at the sampled values with a negligible computational cost. The simulations conducted on the IEEE 57-bus system, to which correlated renewable generation are attached, reveal the excellent performance of the proposed method. © 2020 IEEE.

关键词： Monte Carlo methods

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Probabilistic load-margin assessment using vine copula and gaussian process emulation

arXiv

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arXiv 2020年

作者： Xu, Yijun Karra, Kiran Mili, Lamine Korkali, Mert Chen, Xiao Hu, Zhixiong Bradley Department of Electrical and Computer Engineering Virginia Tech Northern Virginia Center Falls ChurchVA22043 United States Applied Physics Lab Johns Hopkins University BaltimoreMD21218 United States Computational Engineering Division Lawrence Livermore National Laboratory LivermoreCA94550 United States Center for Applied Scientific Computing Lawrence Livermore National Laboratory LivermoreCA94550 United States Department of Statistics University of California-Santa Cruz Santa CruzCA95064 United States

The increasing penetration of renewable energy along with the variations of the loads bring large uncertainties in the power system states that are threatening the security of power system planning and operation. Facing these challenges, this paper proposes a cost-effective, nonparametric method to quantify the impact of uncertain power injections on the load margins. First, we propose to generate system uncertain inputs via a novel vine copula due to its capability in simulating complex multivariate highly dependent model inputs. Furthermore, to reduce the prohibitive computational time required in the traditional Monte-Carlo method, we propose to use a nonparametric, Gaussian-process-emulator-based reduced-order model to replace the original complicated continuation power-flow model. This emulator allows us to execute the time-consuming continuation power-flow solver at the sampled values with a negligible computational cost. The simulations conducted on the IEEE 57-bus system, to which correlated renewable generation are attached, reveal the excellent performance of the proposed method. Copyright © 2020, The Authors. All rights reserved.

关键词： Gaussian distribution

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Rapid radio: A framework for human-assisted signal classification and receiver implementation

Rapid radio: A framework for human-assisted signal classific...

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Jorge Surís Adolfo Recio Peter Athanas Configurable Computing Lab Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA

ISBN: (纸本)9781424444946

An analysis-based framework for the rapid development of a radio receiver for signals with unknown parameters is pro-posed, exploiting the reconfiguration capabilities of FPGAs. The framework guides a non-expert user through the process of signal classification and FPGA-based receiver implementation. System efficiency is traded off with implementation time in order to allow fast radio creation. A set of high-level transformations are applied to the unknown signal based on different hypothesis about the modulation scheme. The results of the transformations are presented to the user, who can steer the process of analysis. The parameters of the radio are then mapped by means of an Implementation Engine to modules implemented in a general purpose FPGA-based receiver.

关键词： Pattern classification Receivers Signal analysis Field programmable gate arrays Signal design Prototypes Graphical user interfaces Engines Data mining Phase modulation

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Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip

Metawire: Using FPGA configuration circuitry to emulate a Ne...

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International Conference on Field Programmable Logic and Applications

作者： M. Shelburne C. Patterson P. Athanas M. Jones B. Martin R. Fong Bradley Department of Electrical & Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

While there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.

关键词： Field programmable gate arrays Magnetic cores Throughput Bandwidth Random access memory Routing Wires

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An efficient run-time router for connecting modules in FPGAS

An efficient run-time router for connecting modules in FPGAS

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International Conference on Field Programmable Logic and Applications

作者： Jorge Suris Cameron Patterson Peter Athanas Bradley Department of Electrical and Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.

关键词： Routing Databases Switches Field programmable gate arrays Wire Delay Propagation delay

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An 8 GHz ultra wideband transceiver prototyping testbed

An 8 GHz ultra wideband transceiver prototyping testbed

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16th Intetrnational Workshop on Rapid System Prototyping, RSP 2005

作者： Agarwal, Deepak Anderson, Christopher R. Athanas, Peter M. Configurable Computing Lab. Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA 24061 United States Mobile and Portable Radio Research Group Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA 24061 United States

ISBN: (纸本)0769523617

Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This paper presents a testbed for the design of an impulse-based ultra wideband communication system. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. The output of each ADC is in a different clock domain, with clocks offset in increments of 125ps. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non-real time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The non-real time component uses the internal Block RAMs to store a set of samples and one of the PowerPC cores to process the data offline, to minimize logic resource usage. The real-time part uses distributed memory to store incoming data and processes it using hardwired multipliers and FPGA logic cells. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s. © 2005 IEEE.

关键词： Rapid prototyping

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An 8 GHz ultra wideband transceiver prototyping testbed

An 8 GHz ultra wideband transceiver prototyping testbed

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International Workshop on Rapid System Prototyping (RSP)

作者： D. Agarwal C.R. Anderson P.M. Athanas Configurable Computing Lab Virginia Polytechnic Institute and State University Blacksburg VA USA Mobile and Portable Radio Research Group Bradley Department of Electrical Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA

Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This paper presents a testbed for the design of an impulse-based ultra wideband communication system. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. The output of each ADC is in a different clock domain, with clocks offset in increments of 125 ps. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non-real time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The non-real time component uses the internal block RAMs to store a set of samples and one of the PowerPC cores to process the data offline, to minimize logic resource usage. The real-time part uses distributed memory to store incoming data and processes it using hardwired multipliers and FPGA logic cells. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s.

关键词： Ultra wideband technology Transceivers Prototypes Testing Field programmable gate arrays Software radio Sampling methods Clocks Signal processing Logic

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A comparative study of the suitability of a custom computing machine and a VLIW DSP for use in 3G applications

A comparative study of the suitability of a custom computing...

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IEEE Workshop on Signal Processing Systems (SIPS)

作者： J. Neel S. Srikanteswara J.H. Reed P.M. Athanas Mobile and Portable Radio Research Group Bradley Department of Electrical and Computer Engineering Virginia Technology USA Configurable Computing Lab Bradley Department of Electrical and Computer Engineering Virginia Technology USA

As wireless communications advances, the complexity of waveform processing places an ever increasing demand on baseband processing resources. As this is a difficult problem for traditional processing solutions to address, many have looked to reconfigurable computing as a solution. For 3G systems, whose intense processing requirements exacerbate these problems, we have previously proposed in (S. Srikanteswara et al, Soft Radio Impl. for 3G and Future High Data Rate Syst., Globecom 2001) the use of custom computing machines (CCMs), also known as adaptive computing machines (ACMs). This paper introduces a method for measuring processor performance which is independent of chip architecture. This method is then used to perform a comparative analysis on the suitability of Virginia Tech's Stallion CCM and Texas, Instrument's TMS320C6201 processor for use in 3G applications.

关键词： VLIW Digital signal processing computer architecture Application software Semiconductor device measurement Field programmable gate arrays Hardware Software radio Baseband Analog integrated circuits

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ASICs, processors, and configurable computing

ASICs, processors, and configurable computing

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： B.L. Hutchings Configurable Computing Lab Department of Electrical and Computer Engineering Brigham Young University Provo UT USA

Summary form only given. It is often suggested that configurable computing represents a new computational middle ground that fills the existing void between conventional microprocessors and ASICs. This point of view is based upon the observation that FPGAs share some similarities with both processors and ASICs. FPGAs are seen as similar to processors because they are customized in the field by the end user by downloading configuration data into the device. They can also be seen as similar to ASICs because they can implement high performance, application specific circuits. It is hoped that if configurable computing can be shown to be similar to conventional processors, it will be possible to borrow microprocessor architecture and compilation techniques for use in the configurable computing community.

关键词： Application specific integrated circuits Field programmable gate arrays Microprocessors Amplitude shift keying Performance gain Parallel processing Distributed computing computer architecture computer languages Circuit synthesis

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