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2009 IEEE/RSJ International Conference on Intelligent Robots and Systems

作者： Damjan Miklic Stjepan Bogdan Sanjin Nestic Rafael Fierro Faculty of Electrical Engineering and Computing University of Zagreb Zagreb Croatia MARHES Lab Electrical & Computer Engineering Department University of New Mexico Albuquerque NM USA Electrical and Computer Engineering Department University of New Mexico

In this paper we present a formation reconfiguration methodology designed for controlling groups of autonomous agents in environments densely populated with obstacles. Our approach is based on abstracting the group of agents by a discrete rectangular grid. Agent and obstacle positions are mapped onto the formation grid. Then, collision free formation transition trajectories are computed using discrete event scheduling techniques that have been well-established in the manufacturing systems domain. The main contribution of this paper is a unified formation control framework that explicitly takes obstacles into account. Using discrete event system analysis tools we show that our approach guarantees convergence to the desired formation while avoiding obstacles and inter-agent collisions.

关键词： Control systems Robot kinematics Navigation Convergence Multiagent systems Processor scheduling Productivity Robot sensing systems Robust stability Stability analysis

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Adverse effects of template-based warping on spatial FMRI analysis

Adverse effects of template-based warping on spatial FMRI an...

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Medical Imaging 2009: Biomedical Applications in Molecular, Structural, and Functional Imaging

作者： Ng, Bernard Abugharbieh, Rafeef McKeown, Martin J. Biomedical Signal and Image Computing Lab Department of Electrical and Computer Engineering Vancouver BC V6T 1Z4 Canada The University of British Columbia Vancouver BC V6T 1Z4 Canada

ISBN: (纸本)9780819475138

Conventional voxel-based group analysis of functional magnetic resonance imaging (fMRI) data typically requires warping each subject's brain images onto a common template to create an assumed voxel correspondence. The implicit assumption is that aligning the anatomical structures would correspondingly align the functional regions of the subjects. However, due to anatomical and functional inter-subject variability, mis-registration often occurs. Moreover, wholebrain warping is likely to distort the spatial patterns of activation, which have been shown to be important markers of task-related activation. To reduce the amount of mis-registration and distortions, warping at the brain region level has recently been proposed. In this paper, we investigate the effects of both whole-brain and region-level warping on the spatial patterns of activation statistics within certain regions of interests (ROIs). We have chosen to examine the bilateral thalami and cerebellar hemispheres during a bulb-squeezing experiment, as these regions are expected to incur taskrelated activation changes. Furthermore, the appreciable size difference between the thalamus and cerebellum allows for exploring the effects of warping on various ROI sizes. By applying our recently proposed 3D moment-based invariant spatial features to characterize the spatial pattern of fMRI activation statistics, we demonstrate that whole-brain warping generally reduced discriminability of task-related activation differences. Applying the same spatial analysis to ROIs warped at the region level showed some improvements over whole-brain warping, but warp-free analysis resulted in the best performance. We hence suggest that spatial analysis of fMRI data that includes spatial warping to a common space must be interpreted with caution. © 2009 SPIE.

关键词： Chemical activation

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From blind to quantitative steganalysis

From blind to quantitative steganalysis

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Media Forensics and Security

作者： Pevný, Tomáš Fridrich, Jessica Ker, Andrew D. INPG - Gipsa-Lab. 961 rue de la Houille Blanche 38402 Grenoble France Department of Electrical and Computer Engineering Binghamton University State University of New York United States Oxford University Computing Laboratory Parks Road Oxford OX1 3QD United Kingdom

ISBN: (纸本)9780819475046

Quantitative steganalyzers are important in forensic steganalysis as they can estimate the payload, or, more precisely, the number of embedding changes in the stego image. This paper proposes a general method for constructing quantitative steganalyzers from features used in blind detectors. The method is based on support vector regression, which is used to learn the mapping between a feature vector extracted from the image and the relative embedding change rate. The performance is evaluated by constructing quantitative steganalyzers for eight steganographic methods for JPEG files, using a 275-dimensional feature set. Error distributions of within- and between-image errors are empirically estimated for Jsteg and nsF5. For Jsteg, the accuracy is compared to state-of-the-art quantitative steganalyzers. © 2009 Copyright SPIE - The International Society for Optical engineering.

关键词： Steganography

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Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip

Metawire: Using FPGA configuration circuitry to emulate a Ne...

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International Conference on Field Programmable Logic and Applications

作者： M. Shelburne C. Patterson P. Athanas M. Jones B. Martin R. Fong Bradley Department of Electrical & Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

While there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.

关键词： Field programmable gate arrays Magnetic cores Throughput Bandwidth Random access memory Routing Wires

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An efficient run-time router for connecting modules in FPGAS

An efficient run-time router for connecting modules in FPGAS

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International Conference on Field Programmable Logic and Applications

作者： Jorge Suris Cameron Patterson Peter Athanas Bradley Department of Electrical and Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.

关键词： Routing Databases Switches Field programmable gate arrays Wire Delay Propagation delay

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IEEE Transactions on Haptics: Editorial

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IEEE Transactions on Haptics 2008年第1期1卷 2-8页

作者： Edward Colgate, J. Lederman, Susan Prattichizzo, Domenico Barbagli, Federico Basdogan, Cagatay Buss, Martin Ernst, Marc Frisoli, Antonio Gillespie, Brent Grant, Danny Harders, Matthias Hayward, Vincent Jones, Lynette Kajimoto, Hiroyuki Kappers, Astrid Kheddar, Abderrahmane Lin, Ming C. MacLean, Karon Miller, Brian Noma, Haruo Okamura, Allison M. O'Malley, Mareia Ryu, Jeha Tan, Hong Z. Yokokohji, Yasuyoshi Department of Psychology School of Computing Queen's University Canada IEEE Robotics and Automation Society Tübingen Germany Stanford University's Computer Science Department Tübingen Germany Institute of Automatic Control Engineering Technische Universität München Germany Independent Research Group Multisensory Perception and Action Max Planck Institute for Biological Cybernetics Tübingen Germany Department of Applied Mechanics SSSA Japan Research Division Virtual Reality and Telerobotic Systems PERCRO Laboratory Japan Department of Mechanical Engineering Japan Department of Robotics McGill University Canada Computer Vision Lab ETH Zurich Japan Virtual Reality in Medicine Group Japan IEEE CS/RAS Technical Committee on Haptics Japan Department of Electrical and Computer Engineering McGill University Canada Department of Mechanical Engineering MIT Japan University of Electro-Communications Japan Department of Physics and Astronomy Utrecht University Netherlands University of Evry France Chapel Hill United States Department of Computer Science University of British Columbia Canada ATR Knowledge Science Lab United Kingdom Department of Mechanical Engineering Denmark Johns Hopkins University United States Laboratory for Computational Sensing and Robotics United Kingdom Engineering Research Center for Computer-Integrated Surgical Systems and Technology United States Mechanical Engineering and Materials Science Department Rice University United States Korea Republic of Department of Electrical and Computer Engineering Mechanical Engineering and Psychological Sciences Purdue University United States Department of Mechanical Engineering and Science Graduate School of Engineering Kyoto University Japan

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A secure quorum based membership mechanism for p2p systems

A secure quorum based membership mechanism for p2p systems

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12th Americas Conference on Information Systems, AMCIS 2006

作者： Liebau, Nicolas C. Heckmann, Oliver Kovacevic, Aleksandra Tafreschi, Omid Fidler, Markus Mauthe, Andreas Steinmetz, Ralf Multimedia Communications Lab Technische Universität Darmstadt Germany IT-Security Group Technische Universität Darmstadt Germany Department of Electrical and Computer Engineering University of Toronto Canada Computing Department Lancaster University United Kingdom Technische Universität Darmstadt Germany

ISBN: (纸本)9781604236262

Closed user group based on a Peer-to-Peer system require a membership mechanism that is fully decentralized. Several suggestions have been made in the literature. However, the proposed mechanisms have some significant drawbacks since any peer can easily bypass the proposed membership mechanism. In this paper we present a new fully decentralized and secure membership mechanism for Peer-to-Peer systems. A quorum of peers decides about membership requests from new peers. In order to prevent the requesting peer from manipulating the membership decision two mechanisms are applied: (1) The quorum peers must make there membership decision unanimously. This is sufficient to guarantee a correct membership decision, if a fraction of the peers in the P2P system is honest and if the quorum peers are selected in a random manner. (2) In order to ensure a random selection of the quorum peer a random value is created in a distributed way that is used to select the quorum. It can be verified, that the quorum was correctly selected. The presented mechanism is evaluated in terms of the offered security and the created traffic overhead.

关键词： Access control

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InfoShield: a security architecture for protecting information usage in memory

InfoShield: a security architecture for protecting informati...

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IEEE Symposium on High-Performance computer Architecture

作者： W. Shi J.B. Fryman G. Gu H.-H.S. Lee Y. Zhang J. Yang School of Electrical and Computer Engineering Georgia Tech College of Computing Georgia Institute of Technology Programming System Lab Corporate Technology Intel Corporation USA Department of Computer Science University of Pittsburgh USA Department of Computer Science and Engineering University of California Riverside USA

Cyber theft is a serious threat to Internet security. It is one of the major security concerns by both network service providers and Internet users. Though sensitive information can be encrypted when stored in non-volatile memory such as hard disks, for many e-commerce and network applications, sensitive information is often stored as plaintext in main memory. Documented and reported exploits facilitate an adversary stealing sensitive information from an application's memory. These exploits include illegitimate memory scan, information theft oriented buffer overflow, invalid pointer manipulation, integer overflow, password stealing Trojans and so forth. Today's computing system and its hardware cannot address these exploits effectively in a coherent way. This paper presents a unified and lightweight solution, called InfoShield that can strengthen application protection against theft of sensitive information such as passwords, encryption keys, and other private data with a minimal performance impact. Unlike prior whole memory encryption and information flow based efforts, InfoShield protects the usage of information. InfoShield ensures that sensitive data are used only as defined by application semantics, preventing misuse of information. Comparing with prior art, InfoShield handles a broader range of information theft scenarios in a unified framework with less overhead. Evaluation using popular network client-server applications shows that InfoShield is sound for practical use and incurs little performance loss because InfoShield only protects absolute, critical sensitive information. Based on the profiling results, only 0.3% of memory accesses and 0.2% of executed codes are affected by InfoShield.

关键词： Information security Protection Cryptography computer security IP networks Web and internet services Nonvolatile memory Hard disks Buffer overflow Hardware

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An 8 GHz ultra wideband transceiver prototyping testbed

An 8 GHz ultra wideband transceiver prototyping testbed

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16th Intetrnational Workshop on Rapid System Prototyping, RSP 2005

作者： Agarwal, Deepak Anderson, Christopher R. Athanas, Peter M. Configurable Computing Lab. Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA 24061 United States Mobile and Portable Radio Research Group Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA 24061 United States

ISBN: (纸本)0769523617

Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This paper presents a testbed for the design of an impulse-based ultra wideband communication system. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. The output of each ADC is in a different clock domain, with clocks offset in increments of 125ps. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non-real time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The non-real time component uses the internal Block RAMs to store a set of samples and one of the PowerPC cores to process the data offline, to minimize logic resource usage. The real-time part uses distributed memory to store incoming data and processes it using hardwired multipliers and FPGA logic cells. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s. © 2005 IEEE.

关键词： Rapid prototyping

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Higher radix floating-point representations for FPGA-based arithmetic

Higher radix floating-point representations for FPGA-based a...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： B. Catanzaro B. Nelson Electrical and Computer Engineering Department Configurable Computing Laboratory Provo UT USA

FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations. The general computing world settled on binary floating-point representations over three decades ago, and more recently, the FPGA community followed their example. Binary representations were chosen to maximize numerical accuracy per bit of data, however, the unique nature of FPGA-based computation makes numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a given floating-point representation. In this paper, we show that higher radix floating-point representations are well suited to FPGA-based computations, especially high precision calculations which require the support of denormalized numbers. Higher radix representations use FPGA resources more efficiently. For example, a hexadecimal floating-point adder has a 30% smaller area-time product than its binary counterpart, while still delivering equal worst-case and better average-case numerical accuracy. Contrary to established belief, higher radix representations are useful for FPGA applications requiring IEEE 754 compliance, since they can deliver superior numerical performance while still using less FPGA resources.

关键词： Floating-point arithmetic Field programmable gate arrays Costs Throughput Hardware computer architecture Design engineering laboratories Delay Fixed-point arithmetic

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