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A Web Scraping Algorithm to Improve the Computation of the Maximum Common Subgraph

A Web Scraping Algorithm to Improve the Computation of the M...

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18th International Conference on Software Technologies, ICSOFT 2023

作者： Calabrese, Andrea Cardone, Lorenzo Licata, Salvatore Porro, Marco Quer, Stefano DAUIN Department of Control and Computer Engineering Politecnico di Torino Turin Italy

ISBN: (纸本)9789897586651

The Maximum Common Subgraph, a generalization of subgraph isomorphism, is a well-known problem in the computer science area. Albeit being NP-complete, finding Maximum Common Subgraphs has countless practical applications, and researchers are continuously exploring scalable heuristic approaches. One of the state-of-the-art algorithms to solve this problem is a recursive branch-and-bound procedure called McSplit. The algorithm exploits an intelligent invariant to pair vertices with the same label and adopts an effective bound prediction to prune the search space. However, McSplit original version uses a simple heuristic to pair vertices and to build larger subgraphs. As a consequence, a few researchers have already focused on improving the sorting heuristics to converge faster. This paper concentrate on these aspects and presents a collection of heuristics to improve McSplit and its state-of-the-art variants. We present a sorting strategy based on the famous PageRank algorithm, and then we mix it with other approaches. We compare all the heuristics with the original McSplit procedure, and against each other. In particular, we distinguish the heuristics based on the node degree and novel ones based on the PageRank algorithm. Our experimental section shows that PageRank can improve both McSplit and its variants significantly regarding convergence speed and solution size. © 2024 by SCITEPRESS – Science and Technology Publications, Lda.

关键词： Graph algorithms

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Improving CNN Runtime Robustness Against Soft Errors by Dropout Layer Optimization

Improving CNN Runtime Robustness Against Soft Errors by Drop...

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Latin American Test Workshop, LATW

作者： Robert Limas Sierra Giuseppe Esposito Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Politecnico di Torino - Department of Control and Computer Engineering (DAUIN)

ISBN: (数字)9781665477635

ISBN: (纸本)9781665477642

Convolutional Neural Networks (CNNs) have shown exceptional effectiveness in complex and data-intensive domains such as image and video processing, conversational systems, and healthcare. Moreover, sectors like High-Performance Computing and safety-critical applications, including automotive, aerospace, and autonomous robotics, impose stringent requirements on energy efficiency, performance, and robustness. However, modern semiconductor technologies are increasingly vulnerable to faults, which can degrade CNN performance and potentially result in catastrophic failures. This work explores the impact of regularization techniques (dropout layer) in enhancing the inference robustness of CNN models against soft errors. We analyzed soft error impacts on five widely adopted CNN architectures, each trained with ten different dropout rates. Our experimental results reveal that optimizing the dropout rate during training can improve the in-field robustness of CNN models by up to 12% compared to baseline configurations under soft error conditions. Additionally, fine-tuning this architectural parameter can lead to accurary improvements of up to 10%.

关键词： Training Accuracy Runtime computer architecture Medical services Robustness Hardware Convolutional neural networks Robots Optimization

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About the Functional In-Field Self-Testing of AI Accelerators

About the Functional In-Field Self-Testing of AI Accelerator...

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Latin American Test Workshop, LATW

作者： Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Robert Limas Sierra Matteo Sonza Reorda Politecnico di Torino - Department of Control and Computer Engineering (DAUIN)

ISBN: (数字)9781665477635

ISBN: (纸本)9781665477642

1 1 Work supported by the National Resilience and Recovery Plan (PNRR) through the National Center for HPC, Big Data and Quantum *** Learning Accelerators (DLA) are pervasive hardware units in modern applications, including safety critical systems such as Automotive, Aerospace, Robotics, and health monitoring systems. Therefore, it is crucial to guarantee their reliability during the mission operation of any of these applications, as a failure can produce catastrophic results (e.g., loss of human lives). In fact, modern semiconductor technologies used to implement DLAs can be affected by faults due to several phenomena, such as aging, process variation, or manufacturing defects. Periodic testing and functional testing strategies have demonstrated their utility and effectiveness on DLA accelerators in spotting faults arising during the in-field operation of the system. Nonetheless, these approaches can have significant testing times and memory footprint overheads, making them hard to apply during the online operation of large-size accelerators. This work proposes an effective strategy for generating efficient functional test patterns for computational units in DLA accelerators by reducing the required testing time (43×) and memory footprints (3.3×) compared with literature solutions. Moreover, our strategy provides diagnostic capabilities for identifying defective units (e.g., multipliers).

关键词： Quantum computing Memory management AI accelerators Built-in self-test Hardware Manufacturing Reliability Robots Monitoring Resilience

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Analyzing the Structural and Operational Impact of Faults in Floating-Point and Posit Arithmetic Cores for CNN Operations

Analyzing the Structural and Operational Impact of Faults in...

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IEEE European Test Symposium (ETS)

作者： Josie E. Rodriguez Condia Juan-David Guerrero-Balaguera Robert Limas Sierra Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

ISBN: (数字)9798350349320

ISBN: (纸本)9798350349337

1 This work reports a first attempt to evaluate the fine-grain impact of permanent faults in the structures of arithmetic hardware cores implementing two number formats (Posit and FP). We assess and analyze errors in the cores for two operations (Add, and Multiply), which are the most used in several modern applications, including machine learning. The results show that Posit cores are structurally more vulnerable to fault propagation and induce more output corruptions than FP cores (from 3.3% up to 6.2%). Moreover, we found that the average absolute error in faulty FP cores is higher by up to 2 orders of magnitude than in Posit ones.

关键词： Europe Machine learning Hardware Circuit faults Reliability Arithmetic

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Analyzing the Impact of Scheduling Policies on the Reliability of GPUs Running CNN Operations

Analyzing the Impact of Scheduling Policies on the Reliabili...

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VLSI Test Symposium

作者： Robert Limas Sierra Juan-David Guerrero-Balaguera Francesco Pessia Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

ISBN: (数字)9798350363784

ISBN: (纸本)9798350363791

The programming flexibility and parallelism of Graphics Processing Units (GPUs) contribute to their effective adoption in complex and data-intensive fields like Machine Learning, especially in the deployment of Convolutional Neural Networks (CNNs). CNNs are also used in some safety-critical applications with severe reliability constraints, such as autonomous driving and robotics. Modern GPUs efficiently combine hardware schedulers controllers and in-chip accelerators (e.g., Tensor Core Units, or TCUs) to enhance CNN’s performance. Interestingly, fine-grain reliability analyses combining the operation of task scheduling policies in GPUs and TCUs have remained unexplored. This work analyses the reliability impact of scheduling policies on GPUs when permanent faults affect TCUs, during the execution of CNN operations. We developed a configurable architectural GPU model (in terms of clusters and parallel cores) that implements five selectable scheduling policies and supports the instruction-accurate execution of TCUs. Our results indicate that the GPU’s architecture and the scheduling policy play a crucial role in the application’s corruption from faulty TCUs. From the experiments, we found that some policies can reduce the corruption effects by up to 22% for large GPUs. In addition, we evaluated the dynamic variability of the scheduling policies and their complexity on identifying deterministic effects on the application’s outputs.

关键词： Tensors Graphics processing units computer architecture Very large scale integration Programming Dynamic scheduling Software

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Deep-Learning-Based Onset Time Precision in Acoustic Emission Non-Destructive Testing

Deep-Learning-Based Onset Time Precision in Acoustic Emissio...

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2024 IEEE International Workshop on Metrology for Living Environment, MetroLivEnv 2024

作者： Melchiorre, Jonathan D'Amato, Leo Agostini, Federico Manuello, Amedeo Politecnico di Torino Department of Structural Geotechnical and Building Engineering Turin Italy Politecnico di Torino DAUIN Department of Control and Computer Engineering Turin Italy University of Padua Department of Physics and Astronomy Padua Italy

ISBN: (纸本)9798350385014

To investigate the actual health status and mechanical properties of structural materials, both direct and/or indirect investigation procedures can be used. The acoustic emission (AE) method is a non-destructive indirect structural health monitoring method based on the analysis of the elastic wave propagation inside the material under study induced during cracks and micro-cracks coalescence, opening, and formation process. To capture reliable ultrasonic elastic waveform data, piezoelectric sensors are typically employed which are directly and firmly fixed and attached to the specimen under study. For identifying the region of crack formation, thus the position of structural damage in its early stage, at least four sensors must be employed simultaneously. Furthermore, the identification of the onset time is crucial to accomplishing this task. In this study, the authors proposed a deep-learning-based solution based on a U-net architecture for identifying onset time with a method attempting to overcome the existing limitations of traditional threshold-based methods. The onset time precision obtained with this artificial intelligence-based (AI) paradigm is discussed on an acknowledged dataset available in the literature based on Pencil Lead Break (PLB) data, commonly used as a benchmark in the AE field. Finally, the method is tested on some real AE signals acquired during laboratory testing of reinforced concrete specimens. The results demonstrated the actual potential of the proposed AI-based method in future real-time monitoring real- world applications. © 2024 IEEE.

关键词： Structural health monitoring

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A Micro Architectural Events Aware Real-Time Embedded System Fault Injector

A Micro Architectural Events Aware Real-Time Embedded System...

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Latin American Test Workshop, LATW

作者： Enrico Magliano Alessio Carpegna Alessadro Savino Stefano Di Carlo Department of Control and Computer Engineering(DAUIN) Politecnico di Torino Turin Italy

ISBN: (数字)9798350365559

ISBN: (纸本)9798350365566

In contemporary times, the increasing complexity of the system poses significant challenges to the reliability, trustworthiness, and security of the Safety-Critical Real-Time Embedded Systems (SACRES). Key issues include the susceptibility to phenomena such as instantaneous voltage spikes, electromagnetic interference, neutron strikes, and out-of-range temperatures. These factors can induce switch state changes in transistors, resulting in bit-flipping, soft errors, and transient corruption of stored data in memory. The occurrence of soft errors, in turn, may lead to system faults that can propel the system into a hazardous state. Particularly in critical sectors like automotive, avionics, or aerospace, such malfunctions can have real-world implications, potentially causing harm to *** paper introduces a fault injector designed with the novelty to facilitate the monitoring, aggregation, and examination of micro-architectural events. This is achieved by harnessing the microprocessor’s Performance Monitoring Unit (PMU) and the debugging interface, explicitly focusing on ensuring the repeatability of fault injections. The fault injection methodology targets bit-flipping within the memory system, affecting CPU registers and RAM. The outcomes of these fault injections enable a thorough analysis of the impact of soft errors in the final output and timing predictability demanded by SACRES.

关键词： Embedded systems Random access memory Voltage Real-time systems Phasor measurement units Registers Timing

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Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies

Evaluating Different Fault Injection Abstractions on the Ass...

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Asian Test Symposium (ATS)

作者： Giuseppe Esposito Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy

ISBN: (数字)9798331529161

ISBN: (纸本)9798331529178

1 The reliability of Neural Networks has gained significant attention, prompting efforts to develop SW-based hardening techniques for safety-critical scenarios. However, evaluating hardening techniques using application-level fault injection (FI) strategies, which are commonly hardware-agnostic, may yield misleading results. This study for the first time compares two FI approaches (at the application level (APP) and instruction level (ISA)) to evaluate deep neural network SW hardening strategies. Results show that injecting permanent faults at ISA (a more detailed abstraction level than APP) changes completely the ranking of SW hardening techniques, in terms of both reliability and accuracy. These results highlight the relevance of using an adequate analysis abstraction for evaluating such techniques.

关键词： Degradation Fault tolerance Accuracy Simulation Fault tolerant systems Artificial neural networks Color Reliability engineering Safety Artificial intelligence

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Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs

Analyzing the Impact of Different Real Number Formats on the...

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IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Robert Limas Sierra Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

1 Modern Graphics Processing Units (GPUs) boost the execution of tiled matrix multiplications by extensively using in-chip accelerators (Tensor Core Units or TCUs). Unfortunately, cutting-edge semiconductor technologies are increasingly prone to fault defects. Indeed, faults may affect TCUs when processing massive amounts of data under classical floating-point formats, raising reliability concerns when used in the safety-critical and High-Performance Computing (HPC) domains. In this scenario, the characterization of faulty TCUs supporting different arithmetic formats is still missed. This work for the first time quantitatively evaluates the effects of hardware faults arising in TCU structures when using two different formats for real number representation (i.e., Floating-Point and Posit). For the experimental evaluation, we resort to an architectural description of a TCU core (PyOpenTCU) and perform 60 fault simulation campaigns, injecting 57,344 faults per campaign and requiring around 24 days of computation. The experimental results indicate a relation between the corrupted spatial areas in the output matrices and the TCU’s scheduling policies. Moreover, the numeric analysis shows that hardware faults in TCUs in most cases affect up to 2 bits in the output results for both considered formats. The results also demonstrate that the Posit formats are less affected by faults than Floating-Point formats by up to one order of magnitude.

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Optimizing the Analysis and Evaluation of Logic Simulation Workloads in HPC Systems

Optimizing the Analysis and Evaluation of Logic Simulation W...

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International Conference on Application of Information and Communication Technologies (AICT)

作者： Robert Limas Sierra Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

The increasing transistor density and the data-intensive nature of modern applications impede the development of exhaustive validations and reliability estimations in feasible times. Traditional evaluation strategies use simulation-based Fault Injection (FI), demanding considerable computational power. Thus, computation in High-Performance Computing (HPC) systems has become relevant. However, most FIs workloads follow sequential behaviors, impacting their effectiveness and efficiency in HPCs. This work proposes a method to analyze FI workloads and exploit HPCs. The technique uses container managers to boost the throughput and performance of sequential FI workloads used in dependability analyses. Our results demonstrate that Logic Simulation Workloads performance can improve up to 600 times.

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