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A Reliability-aware Environment for Design Exploration for GPU Devices

A Reliability-aware Environment for Design Exploration for G...

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IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Robert Limas Sierra Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

1 Nowadays, GPU platforms have gained wide importance in applications that require high processing power. Unfortunately, the advanced semiconductor technologies used for their manufacturing are prone to different types of faults. Hence, solutions are required to support the exploration of the resilience to faults of different architectures. Based on this motivation, this work presents an environment dedicated to the analysis of the impact of permanent faults on GPU platforms. This environment is based on GPGPU-Sim, with the objective of exploiting the configuration features of this tool and, thus, analyzing the effects of faults when changing the target architecture. To validate the environment and show its usability, a fault campaign has been carried out where three different GPU architectures (Kepler, Volta, and Turing) were used. In addition, each GPU has been modified with an arbitrary number of parallel processing cores (or SMs). Three representative applications (Vector Add, Scalar Product, and Matrix Multiply) were executed on each GPU, and the behavior of each architecture in the presence of permanent faults in the functional (i.e., integer unit and floating-point) units was analyzed. This fault campaign shows the usability of the environment and demonstrates its potential use to support decisions on the best architectural parameters for a given application.

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Evaluating the Impact of Transition Delay Faults in GPUs

Evaluating the Impact of Transition Delay Faults in GPUs

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International Conference on VLSI Design

作者： Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

This work proposes a method to evaluate the effects of transition delay faults (TDFs) in GPUs. The method takes advantage of low-level (i.e., RT- and gate-level) descriptions of a GPU to evaluate the effects of transition delay faults in GPUs, thus paving the way to model them as errors at the instruction level, which can contribute to the resilience evaluations of large and complex applications. For this purpose, the paper describes a setup that efficiently simulates transition delay faults. The results allow us to compare their effects with stuck-at-faults (SAFs) and perform an error classification correlating these faults as instruction-level errors. We resort to an open-source model of a GPU (FlexGripPlus) and a set of workloads for the evaluation. The experimental results show that, according to the application code style, TDFs can compromise the operation of an application from 1.3 to 11.63 times less than SAFs. Moreover, for all the analyzed applications, a considerable percentage of sites of the Integer (5.4% to 51.7%), Floating-point (0.9% to 2.4%), and Special Function unit (17.0% to 35.6%) can become critical if affected by a SAF or TDF. Finally, a correlation between the fault's impact from both fault models and the instructions executed by the applications reveals that SAFs in the functional units are more prone (from 45.6% to 60.4%) to propagate errors at the software level for all units than TDFs (from 17.9% to 58.8%).

关键词： Embedded systems Correlation Codes Graphics processing units Very large scale integration Logic gates Software

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Evaluating the Reliability of Supervised Compression for Split Computing

Evaluating the Reliability of Supervised Compression for Spl...

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VLSI Test Symposium

作者： Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Marco Levorato Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy Computer Science Department University of California Irvine US

ISBN: (数字)9798350363784

ISBN: (纸本)9798350363791

Recent advances in Internet-of-things (IoT) and 5G infrastructures promote new computational paradigms such as Split Computing (SC) for deploying Deep Neural Networks (DNNs) on mobile applications. In SC, DNNs are partitioned into head and tail sub-models that are executed on the mobile device and cloud/edge servers, respectively. Modern SC models resort to head compression techniques to balance energy consumption, transmission data, and model size while preserving the outstanding accuracy of large state-of-the-art DNNs. These features make SC DNNs suitable for mobile applications, including safety-critical systems (e.g., self-driving vehicles, autonomous robots, and healthcare equipment), where reliability is a paramount factor mandated by strict safety standards. Despite there are many studies available about the reliability of DNNs, the SC models are still unexplored, especially when hardware faults threaten the operation of a mobile device. In this work, we present for the first time $i)$ an application-level fault injection strategy for modeling hardware faults on mobile GPUs executing SC DNNs and ii) an evaluation of the resilience of supervised compression methods utilized by SC systems. The preliminary results gathered on some representative benchmark networks and configurations show the feasibility and effectiveness of the approach. They also demonstrate that aggressive compression strategies lead to high accuracy degradation $(\approx$ 40%), increasing the overall vulnerability of the DNN and the system.

关键词： Computational modeling Artificial neural networks Tail Very large scale integration Mobile handsets Hardware Data models

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Assessing the Reliability of Different Split Computing Neural Network Applications

Assessing the Reliability of Different Split Computing Neura...

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Latin American Test Workshop, LATW

作者： Giuseppe Esposito Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Marco Levorato Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy Computer Science Department University of California Irvine US

ISBN: (数字)9798350365559

ISBN: (纸本)9798350365566

1 Neural Networks (NNs) are increasingly adopted in many domains. Given their considerable computational expenses required only during inference, it has been proposed that their architecture can be split into two sections (Head and Tail) in a paradigm referred to as Split Computing (SC). The Head section executes the first part of a NN at a mobile device, while a Tail model calculates the missing part of the NN resorting to a server. SC allows a designer to find the optimal configuration, trading off computing load, performance, latency, and power. However, the adoption of SC approaches in safety-critical domains involves strong reliability concerns. This paper introduces an environment allowing to estimate the effects of permanent faults affecting the hardware supporting the execution of the head model, which is the most prone to faults. Results are reported for different NNs and different configurations, demonstrating the effectiveness of the method and paving the way towards the deployment of more resilient SC systems. Our results show that the considered split configurations of all models under test are up to 10% more critically vulnerable to faults than the corresponding original architecture.

关键词： Performance evaluation Sensitivity Computational modeling Neurons Artificial neural networks Tail computer architecture

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Effective Application-level Error Modeling of Permanent Faults on AI Accelerators

Effective Application-level Error Modeling of Permanent Faul...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Francesco Pessia Juan-David Guerrero-Balaguera Robert Limas Sierra Josie E. Rodriguez Condia Marco Levorato Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy Computer Science Department University of California Irvine US

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

The deployment of Machine Learning (ML) applications extensively leverages Matrix Multiplication (MM) operations on modern and advanced accelerators, like Graphic Processing Units (GPUs), which employ Tensor Core Units (TCUs) to optimize MM’s execution efficiently. However, reliability concerns arise in devices with cutting-edge semiconductor technologies (7 nm or less), as faults can compromise some structures (e.g., TCUs) during their operation. In safety-critical applications, this can lead to wrong DNN outcomes and cause unpredictable and unacceptable actions. Thus, the impact evaluation of such faults is crucial to ensure that TCUs and GPUs meet the safety standard requirements (e.g., ISO26262). Currently, the reliability assessment of complex applications concerning hardware faults involves fault injection (FI) campaigns. Unfortunately, low-level FI campaigns might be computationally prohibitive for GPUs when these execute massive applications like DNNs. In this work, we propose an error modeling approach to accurately describe corruptions from permanent faults on TCUs, during the operation of MMs. This approach enables realistic reliability evaluations of computationally expensive MM-based workloads, resulting in a huge acceleration (up to 225X) compared with hardware-level FIs. Our experimental results show a very good accuracy (up to $93 \%$ correlation between our error modeling approach and FI campaigns conducted on TCUs).

关键词： Tensors Computational modeling Machine learning Reliability engineering Safety System analysis and design Standards

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Enhancing the Reliability of Split Computing Deep Neural Networks

Enhancing the Reliability of Split Computing Deep Neural Net...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Giuseppe Esposito Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Marco Levorato Matteo Sonza Reorda Politecnico di Torino - Department of Control and Computer Engineering (DAUIN) Turin Italy Computer Science Department University of California Irvine US

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

Artificial intelligence is becoming increasingly popular for IoT applications in safety-critical fields (e.g., autonomous systems and biomedical, robots). Unfortunately, the inference’s workload process alone increases as the model size grows. To meet the computational power limitations of mobile devices running IoT applications, modern services sometimes resort to the Split Computing paradigm. Split Computing divides the inference process of a Neural Network into Head and Tail for their execution in a mobile device and a server, respectively, which also allows the reduction of the overall IoT device’s computational cost. Nonetheless, Split Computing can be used in safety-critical fields where reliability is crucial, especially when mobile devices have computational and cost restrictions. This paper introduces hardening techniques acting on the software to mitigate the effects of hardware faults on Split Computing models. The proposed hardening techniques consist of i) a bounded activation function whose thresholds are refined by training, and ii) a per-channel bounding of the bottleneck quantization of the split points. To quantitatively assess their effectiveness, we resorted to two different split configurations of a model for image classification. In addition, we considered a Split Computing model for object detection. Our findings indicate that the proposed approaches effectively reduces fault effects by $\mathbf{3. 5 \%}$ for image classifiers and $5.73 \%$ for object detectors when compared with other hardening approaches for general DNNs.

关键词： Training Quantization (signal) Head Computational modeling Object detection Artificial neural networks Mobile handsets

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Special Session: Software-Based Self-Test Generation for RISC-V – Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration –

Special Session: Software-Based Self-Test Generation for RIS...

引用

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Tobias Faller Nikolaos I. Deligiannis Riccardo Cantoro Matteo Sonza Reorda Bernd Becker Department of Computer Science University of Freiburg Freiburg Germany Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy

ISBN: (数字)9798350366884

ISBN: (纸本)9798350366891

Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. Traditionally, the generation of such SBST programs requires time-consuming manual labor in combination with in-depth knowledge of the processor's architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST for a given fault model and, moreover, prove the untestability of certain faults. During generation, a constraint specification Validity Checker Module (VCM) ensures correct, functional SBST behavior. The operating conditions in the field and the processor and system-specific constraints are included in this specification, too, in a highly configurable form. In this paper, we present an intermediate VCM interface to generalize the functional constraint specification on RISC-V processors and apply it to two in-field test-related areas. First, we perform SBST generation for detecting permanent hardware faults (stuck-at) in the ALU and the register file of multiple RISC-V processors. Second, we perform functional untestability analysis for the cell-aware fault model on the same processors. Finally, we synthesize the largest processor core on an FPGA with user-controlled fault injection to demonstrate the subsequent detection via the generated stuck-at SBST to a non-technical audience.

关键词： Fault diagnosis Program processors Runtime Built-in self-test Very large scale integration Software Registers Test pattern generators Field programmable gate arrays Nanotechnology

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Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults

Evaluating the Reliability of Integer Multipliers With Respe...

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IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Nikolaos I. Deligiannis Riccardo Cantoro Matteo Sonza Reorda S. E. D. Habib Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy Department of Electronics and Electrical Communications Engineering Cairo University Giza Egypt

Arithmetic circuits form the foundation of modern digital computation, enabling us to conduct precise mathematical operations and drive the digital age. They are integral components in nearly every digital circuit, such as processors' arithmetic and logic units. Especially in safety-critical domains like automotive and aviation, the flawless operation of these circuits is of paramount importance. This paper presents a case study involving two variants of Dadda multipliers and assesses their intrinsic reliability when affected by permanent hardware faults. We conducted extensive fault injection campaigns on the circuit models under various datasets, presenting the aggregated statistical errors in the form of the mean absolute error (MAE) for each case. Specifically, we performed fault injection campaigns in which the operands are sourced from trained quantized weights of a convolutional neural network, as well as randomly generated sets of integers. The results not only reveal differences between the two circuits but also show significant variations when different datasets are used in the fault injection campaigns.

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Modelling Concurrent RTP Flows for End-to-end Predictions of QoS in Real Time Communications

Modelling Concurrent RTP Flows for End-to-end Predictions of...

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IEEE International Symposium on Multimedia

作者： Tailai Song Paolo Garza Michela Meo Maurizio Matteo Munafò Department of Electronics and Telecommunications Engineering (DET) Politecnico di Torino Turin Italy Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy

ISBN: (数字)9798331511111

ISBN: (纸本)9798331511128

The Real-time Transport Protocol (RTP)-based real-time communications (RTC) applications, exemplified by video conferencing, have experienced an unparalleled surge in popularity and development in recent years. In pursuit of optimizing their performance, the prediction of Quality of Service (QoS) metrics emerges as a pivotal endeavor, bolstering network monitoring and proactive solutions. However, contemporary approaches are confined to individual RTP flows and metrics, falling short in relationship capture and computational efficiency. To this end, we propose Packet-to-Prediction (P2P), a novel deep learning (DL) framework that hinges on raw packets to simultaneously process concurrent RTP flows and perform end-to-end prediction of multiple QoS metrics. Specifically, we implement a streamlined architecture, namely length-free Transformer with cross and neighbourhood attention, capable of handling an unlimited number of RTP flows, and employ a multi-task learning paradigm to forecast four key metrics in a single shot. Our work is based on extensive traffic collected during real video calls, and conclusively, P2P excels comparative models in both prediction performance and temporal efficiency.

关键词： Measurement Deep learning Transport protocols Quality of service Streaming media Predictive models Transformers Real-time systems Surges Videoconferences

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Analysis and Mitigation of Soft-errors in GPU-accelerated Hyperspectral Image Classifiers

Analysis and Mitigation of Soft-errors in GPU-accelerated Hy...

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IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Sergiu-Mohamed Abed Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Gianluca De Lucia Marco Lapegna Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino CASD Scuola Superiore Universitaria Rome Italy Department of Mathematics and Applications University of Naples Federico II

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

This work assesses the reliability of a hyperspectral image classifier for edge devices under transient faults by using a fine-grain strategy based on the Hardware Injection Through Program Transformation (HITPT) technique. The results identified the most vulnerable software parts and the corruption effects due to hardware faults (from 5.1% to 100.0% of accuracy drop). Then, the results supported the adoption of a selective-hardening software mechanism (based on the Duplication with Comparison strategy) to effectively mitigate the most critical effects under limited costs.

关键词： Costs Graphics processing units Reliability engineering Hardware Software Software reliability Circuit faults Transient analysis Principal component analysis Hyperspectral imaging

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