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An Integrated Environment for the Reliability Assessment of CNNs Accelerators Implemented in FPGAs

An Integrated Environment for the Reliability Assessment of ...

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Latin American Test Workshop, LATW

作者： Luis Ariel Mesa Juan-David Guerrero-Balaguera Erika D. Castañeda Ernesto Sanchez Wilson-Javier Pérez-Holguín GIRA Research Group Universidad Pedagogica y Tecnologica de Colombia (UPTC) Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

ISBN: (数字)9798350365559

ISBN: (纸本)9798350365566

This work presents the development of an integrated framework that facilitates the resilience evaluation of CNNs w.r.t. hardware faults by resorting to fault emulation strategies. The proposed framework leverages the flexibility of Field-Programmable Gate-Arrays (FPGAs) to implement and evaluate any DL accelerator architecture. In addition, we describe the detailed procedure to emulate faults inside a DL architecture. We report the cost, simulation time, and hardware overhead required by the proposed technique when using a stream-processing DL accelerator to deploy some of the most relevant layers of LeNet5. The experimental results were gathered in four different FPGA-based platforms, demonstrating the flexibility of the proposed approach.

关键词： Costs Emulation Accelerator architectures Life estimation Logic gates Hardware Reliability

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Constraint-Based Automatic SBST Generation for RISC-V Processor Families

Constraint-Based Automatic SBST Generation for RISC-V Proces...

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IEEE European Test Symposium (ETS)

作者： Tobias Faller Nikolaos I. Deligiannis Markus Schwörer Matteo Sonza Reorda Bernd Becker Department of Computer Science University of Freiburg Freiburg Germany Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy

Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. The creation of such SBST programs often requires time-consuming manual labour that is expensive and requires in-depth knowledge of the processor’s architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST. Constraints for the BMC problem are encoded in a circuit called Validity Checker Module (VCM) and applied during SBST *** this paper, we focus on presenting a VCM architecture and a constraint set that allows building SBSTs that make minimal assumptions about the firmware, targeting hard-to-test faults in the ALU and register file of multiple scalar, in-order RISC-V processor families. The VCM architecture consists of a processor-specific mapping layer and a generic constraint set connected via a well-defined interface. The generic constraint set enforces the desired SBST behaviour, including controlling the processor’s pipeline state, memory accesses, and with that executed instructions, register state, and fault propagations. Using a generic constraint set allows for rapid SBST generation targeting new RISC-V processor families while keeping the generic constraints untouched. Lastly, we evaluate this approach on two RISC-V processor families, namely the DarkRISCV and a proprietary, industrial core showing the portability and strength of the approach, allowing for rapidly targeting new processors.

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Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing

Automating the Generation of Functional Stress Inducing Stim...

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IEEE European Test Symposium (ETS)

作者： Nikolaos I. Deligiannis Tobias Faller Zhou Chenghan Riccardo Cantoro Bernd Becker Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy Department of Computer Science University of Freiburg Freiburg Germany

In the domain of high reliability applications, Burn-In testing (BI) is always present since it is one of the prime countermeasures against the infant mortality phenomenon. Traditional static BI testing proves to be inefficient for modern circuit designs. As the devices’ feature size scales down and their structural and architectural complexity increases, so does the complexity and cost of the BI test. Different BI methods are employed by the industry where stimuli are also applied to the devices under test (DUTs) in order to effectively stress and stimulate all nets of the design. One known industry practice resorts to Design for Testability (DfT) infrastructures (e.g., scan) and is based on the application of test vectors at low frequency to excite the DUT as much as possible with the goal of switching each net of the design at least once. In this paper we consider the case where the layout of the circuit is known and propose two novel methods able to automatically produce functional stimuli to switch pairs of neighboring nodes (i.e., nodes that are placed within a specified distance in the DUT) in short periods of time. This solution has been shown to be able to trigger some latent defects in a circuit better than other methods. As a case study, we target functional units within a RISC-V processor (RI5CY). We show that the functional stimuli generated by the exact method described in the paper are able to achieve optimal results (i.e., the maximum functional switching of neighboring pairs), thus maximizing the chance that their at-speed application can activate weak points in the circuit.

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An Embedded Low-Cost Solution for a Fog Computing Device on the Internet of Things

An Embedded Low-Cost Solution for a Fog Computing Device on ...

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International Conference on Fog and Mobile Edge Computing (FMEC)

作者： Pietro D’Agostino Massimo Violante Gianpaolo Macario Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Torino Italy AROL Closure Systems Torino Italy

The adaptability of devices can be significant for a customer that inserts them in an industrial production line. The ability to modify an object bought along with a machine that can be personalized with its features can change how they want to do measurements for different reasons, like predictive maintenance. Fog computing local centers already exist in the market, but they are usually on-the-shelf products with no margin of change for any user. However, with the usage of Docker and containers, this can change. This paper describes a fog computing local central called Concentrator, which can not only execute its essential functions built-in by the producer but also be customized by the user to add in the elaborations on other external sensors, expanding its capabilities and usage. We wanted to improve the device already tested on a Linux PC on a Raspberry Pi and try its performance and characteristics, seeing if it could be transformed into an embedded architecture and an industrial feature.

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Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors

Automatic Identification of Functionally Untestable Cell-Awa...

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Asian Test Symposium (ATS)

作者： Nikolaos I. Deligiannis Tobias Faller Iacopo Guglielminetti Riccardo Cantoro Bernd Becker Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Turin Italy Department of Computer Science University of Freiburg Freiburg Germany STMicroelectronics Turin Italy

In-field test of microprocessors is a major topic for the industry, especially in the safety-critical domain, where the respective standards mandate high test coverage thresholds. The dominant fault models used are the transition delay and the stuck-at fault model. However, the adoption of very advanced semiconductor technologies to manufacture devices used in safety-critical applications pushes toward considering new fault models that are better suited to catch subtle and age-related defects. Among the other phenomena, latent cell-internal defects emerged as relevant causes for several failures. Hence, the necessity for the Cell-Aware Test (CAT) was born, and the inclusion of the CAT fault model in the latest safety standards. Although CAT amends the issue of the numerous test escapes, it may suffer as well from the presence of functionally untestable faults that may pollute the overall test efficiency with their presence. In this paper, we propose a solution, based on formal methods, for the automatic identification of functionally untestable faults under the Cell-Aware fault model for the case where the DUT is a fully pipelined processor. As a case study, we used the RISC-V processor RI5CY for which we applied the minimum constraints required to ensure a functional behavior to demonstrate the effectiveness and impact of the approach. With the considered constraints, a significant percentage of functionally untestable faults was located in the several modules within the processor. Furthermore, the method allows to flexibly take into account any constraint stemming from the system configuration and the application. The obtained results have been validated by resorting to commercial EDA tools.

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Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs

Analyzing the Architectural Impact of Transient Fault Effect...

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Latin American Test Workshop, LATW

作者： Josie E. Rodriguez Condia Juan-David Guerrero-Balaguera Edwar J. Patiño Núñez Robert Limas Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Universidad Pedagogica y Tecnologica de Colombia (UPTC) - Electronic Engineering School

1 1 This work has been supported by the National Resilience and Recovery Plan (PNRR) through the National Center for HPC, Big Data and Quantum *** Processing Units (GPUs) are crucial in modern safety-critical systems to implement complex and dense algorithms, so their reliability plays an essential role in several domains (e.g., automotive and autonomous machines). In fact, reliability evaluations in GPUs and their internal units are of special interest by their high parallelism and to identify vulnerable structures. In particular, Special Function Unit (SFU) cores, inside GPUs, are highly used in multimedia, scientific computing, and the training of neural networks. However, reliability evaluations in SFUs have remained highly unexplored. This work evaluates the impact of transient faults in the hardware structures of SFUs for GPUs. We focus on evaluating and analyzing two SFU architectures (‘fused’ and ‘modular’) and their relations to energy, area, and reliability impact on GPU workloads. The evaluation resorts to a fine-grain analysis with experiments using an RTL open-source GPU (FlexGripPlus) instrumented with both SFUs. The experimental results on both SFU architectures indicate that modular SFUs are less vulnerable to transient faults (in up to 47% for the analyzed workloads) and are more power efficient (in up to 36.6%) but require additional cost in terms of area (about 27%) in comparison with a fused SFU architecture (base for commercial devices), which seems more vulnerable to faults, but is area efficient.

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Evaluating the Prevalence of SFUs in the Reliability of GPUs

Evaluating the Prevalence of SFUs in the Reliability of GPUs

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IEEE European Test Symposium (ETS)

作者： Josie E. Rodriguez Condia Juan-David Guerrero-Balaguera Edwar J. Patiño Núñez Robert Limas Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Electronic Engineering School Universidad Pedagogica y Tecnologica de Colombia (UPTC)

1 Currently, Graphics Processing Units (GPUs) are extensively used in several safety-critical domains to support the implementation of complex operations where reliability is a major concern. Some internal cores, such as Special Function Units (SFUs), are increasingly adopted, being crucial to achieving the necessary performance in multimedia, scientific computing, and neural network training. Unfortunately, these cores are highly unexplored in terms of their impact on *** this work, we evaluate the incidence of SFUs on the reliability of GPUs when affected by soft errors. First, we analyze the impact of SFU cores on the GPU’s reliability and the running workloads. We resort to applications configured to use or not the SFU cores and evaluate the effect of soft errors by using a software-based fault injection environment (NVBITFI) in an NVIDIA Ampere GPU. Then, we focus on evaluating the impact of soft errors arising in the SFUs. A fine-grain RTL evaluation determines the soft error effects on two SFUs architectures for GPUs (’fused’ and ’modular’). The experiments use an open-source GPU (FlexGripPlus) instrumented with both SFU architectures. The results suggest that workloads using SFUs are more vulnerable to faults (from 1 up to 5 orders of magnitude for the analyzed applications). Moreover, the RTL results show that modular SFUs are less vulnerable to faults (in up to 47% for the analyzed workloads) in comparison with fused SFUs (base of commercial devices), so allowing us to identify the more robust SFU architecture.

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Deep-Learning-Based Onset Time Precision in Acoustic Emission Non-Destructive Testing

Deep-Learning-Based Onset Time Precision in Acoustic Emissio...

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Metrology for Living Environment (MetroLivEn), IEEE International Workshop on

作者： Jonathan Melchiorre Leo D'Amato Federico Agostini Amedeo Manuello Department of Structural Geotechnical and Building Engineering Politecnico di Torino Turin Italy Department of Control and Computer Engineering Politecnico di Torino DAUIN Turin Italy Department of Physics and Astronomy University of Padua Padua Italy

ISBN: (数字)9798350385014

ISBN: (纸本)9798350385021

To investigate the actual health status and mechanical properties of structural materials, both direct and/or indirect investigation procedures can be used. The acoustic emission (AE) method is a non-destructive indirect structural health monitoring method based on the analysis of the elastic wave propagation inside the material under study induced during cracks and micro-cracks coalescence, opening, and formation process. To capture reliable ultrasonic elastic waveform data, piezoelectric sensors are typically employed which are directly and firmly fixed and attached to the specimen under study. For identifying the region of crack formation, thus the position of structural damage in its early stage, at least four sensors must be employed simultaneously. Furthermore, the identification of the onset time is crucial to accomplishing this task. In this study, the authors proposed a deep-learning-based solution based on a U-net architecture for identifying onset time with a method attempting to overcome the existing limitations of traditional threshold-based methods. The onset time precision obtained with this artificial intelligence-based (AI) paradigm is discussed on an acknowledged dataset available in the literature based on Pencil Lead Break (PLB) data, commonly used as a benchmark in the AE field. Finally, the method is tested on some real AE signals acquired during laboratory testing of reinforced concrete specimens. The results demonstrated the actual potential of the proposed AI-based method in future real-time monitoring real- world applications.

关键词： Deep learning Training Acoustic emission Real-time systems Sensors Reliability Task analysis

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Recovering Missing Monitoring Data to Enhance Service Provisioning in the Edge-to-Cloud Continuum

Recovering Missing Monitoring Data to Enhance Service Provis...

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IEEE Conference on Network Softwarization (NetSoft)

作者： Gaetano Francesco Pittalà Cristian Zilli Nicola Di Cicco Gianluca Davoli Alessio Sacco Department of Electrical Electronic and Information Engineering (DEI) University of Bologna Italy Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Italy Department of Electronics Information and Bioengineering (DEIB) Politecnico di Milano Italy

ISBN: (数字)9798350369588

ISBN: (纸本)9798350369595

Efficient service provisioning in the Edge-to-Cloud Continuum is of utmost importance for modern applications. While sensible decisions can be taken if enough monitoring data is collected, maintaining continuous telemetry data streams amidst the continuum’s complexity is challenging. This paper introduces CRISP (reConstructing Resource Information for Service Placement), a solution combining data reconstruction and service placement strategies to optimize decisions despite incomplete monitoring data. CRISP utilizes Convolutional Neural Networks and Long Short-Term Memory models for data reconstruction, integrating them with a heuristic algorithm that selects nodes for service component placement. Numerical results demonstrate CRISP’s efficacy in optimizing service provisioning despite missing data, contributing to enhanced resource utilization and service performance in the considered context.

关键词： Heuristic algorithms Data models Numerical models Complexity theory Telemetry Resource management Convolutional neural networks

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Creation of a Support Software for the Development of a System for Sending and Visualizing FBG Sensor Data for Aerospace Application

Creation of a Support Software for the Development of a Syst...

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IEEE Metrology for Aerospace

作者： Antonio Costantino Marceddu Alessandro Aimasso Antonio Scaldaferri Paolo Maggiore Bartolomeo Montrucchio Matteo D. L. Dalla Vedova Department of Control and Computer Engineering Politecnico di Torino Turin Italy Department of Control and Computer Engineering (DAUIN) Politecnico di Torino Torino Italy Department of Mechanical and Aerospace Engineering Politecnico di Torino Turin Italy Department of Mechanical and Aerospace Engineering (DIMEAS) Politecnico di Torino Torino Italy

Optical fiber-based sensors have rapidly increased their application fields across multiple engineering sectors. Their physical characteristics, including low weight, electrical passivity, immunity to electromagnetic disturbances, and high sensitivity, make them highly suitable for aerospace applications. A flying test bench was recently developed at the Politecnico di Torino to evaluate the performance of optical sensors applied to an aircraft model. To allows their fruition in near real-time, it was necessary to develop a pipeline of software capable of transmitting, saving, and displaying them on the ground. To carry out in-depth tests on their reliability it is necessary to carry out more tests with different sensors and configurations. However, doing flight tests for the sole purpose of testing the data acquisition system is too expensive and impractical. Therefore, it was developed an emulator software that can generate data like that obtained from the real system, saving time and resources. Thanks to it, it is now possible to exploit the complete test bench on the aircraft for the final verification campaign only. The results are therefore very positive and demonstrate the potential of the emulator also for the most recent applications.

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