This paper is concerned with tensor clustering with the assistance of dimensionality reduction approaches. A class of formulation for tensor clustering is introduced based on tensor Tucker decomposition models. In thi...
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ISBN:
(纸本)9781479914821
This paper is concerned with tensor clustering with the assistance of dimensionality reduction approaches. A class of formulation for tensor clustering is introduced based on tensor Tucker decomposition models. In this formulation, an extra tensor mode is formed by a collection of tensors of the same dimensions and then used to assist a Tucker decomposition in order to achieve data dimensionality reduction. We design two types of clustering models for the tensors: PCA Tensor Clustering model and Non-negative Tensor Clustering model, by utilizing different regularizations. The tensor clustering can thus be solved by the optimization method based on the alternative coordinate scheme. Interestingly, our experiments show that the proposed models yield comparable or even better performance compared to most recent clustering algorithms based on matrix factorization.
This paper proposes a hardware error checking approach (CCRC) by using redundancy core for multiprocessor system-on-chip (MPSoC) and describes several main error detection methods based on software-Implemented Hardwar...
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作者:
Clements-Croome, DerekComputer Science Department
Escuela Politecnica Superior Universidad Autonoma de Madrid C/Francisco Tomás y Valiente 28049 Madrid Spain Software Engineering Department
Faculty of Automatics Computers and Electronics University of Craiova Bvd. Decebal 107 200440 Craiova Romania Applied Research Laboratory
Information Science and Technology Division Pennsylvania State University 204 V Applied Science Building University Park PA 16802 United States Systems Engineering Section
Faculty of Technology Policy and Management Delft University of Technology Jaffalaan 5 2628BX Delft Netherlands
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This paper proposes a hardware fault detection approach by using redundancy core for Multiprocessor system-on-chip (MPSoC). The proposed approach insert some error detection code in high level code and remove the calc...
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This paper proposes a hardware fault detection approach by using redundancy core for Multiprocessor system-on-chip (MPSoC). The proposed approach insert some error detection code in high level code and remove the calculation of detection code to the redundancy core of MPSoC. The author compares the proposed approach with several soft-based fault detection methods on fault detection capabilities, area, memory and performance overheads in an experiment platform. The result of comparative evaluation shows that the proposed approach is effective for MPSoC, taking some advantages in flexibility and lower cost.
Runtime testing is a common way to detect faults during normal system operation. To achieve a specific diagnostic coverage runtime testing is also used in safety critical, automotive embedded systems. In this paper we...
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Runtime testing is a common way to detect faults during normal system operation. To achieve a specific diagnostic coverage runtime testing is also used in safety critical, automotive embedded systems. In this paper we...
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Runtime testing is a common way to detect faults during normal system operation. To achieve a specific diagnostic coverage runtime testing is also used in safety critical, automotive embedded systems. In this paper we propose a test architecture to consolidate the hardware resource consumption and timing needs of runtime tests and of application and system tasks in a hard real-time embedded system as applied to the automotive domain. Special emphasis is put to timing requirements of embedded systems with respect to hard real-time and concurrent hardware resource accesses of runtime tests and tasks running on the target system.
作者:
[Systems Research Institute
Polish Academy of Sciences Warsaw and University of Gdansk Warsaw Poland Systems Research Institute
Polish Academy of Sciences Warsaw and Management Academy Warsaw Poland Software Engineering Department
Faculty of Automatics Computers and Electronics University of Craiova Bvd.Decebal Craiova Romania University of Duisburg-Essen
Institute for Computer Science and Business Information Systems (ICB) Practical Computer Science Data Management Systems and Knowledge Representation Essen Germany
PROB is an animation and model checking tool, which supports integrated event-and state-based specifications combining B and CSP. We present an initial strategy for implementing the combined specification model as a c...
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This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in...
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ISBN:
(纸本)9783981080162
This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.
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