This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchro...
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The modeling of computersoftware is complex and error prone. Modeling methods and languages must be usable which implies easy to learn. Cognitive dimensions and grounded theory were used to analyse the usability and ...
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Interaction in a multi-agent system is susceptible to failure. A rigorous development of a multi-agent system must include the treatment of fault-tolerance of agent interactions for the agents to be able to continue t...
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The notation and environment in conceptual modelling transform developers' initial perception about a system to a concrete model. Any usability constraints that the notation and environment impose on the modeling ...
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The notation and environment in conceptual modelling transform developers' initial perception about a system to a concrete model. Any usability constraints that the notation and environment impose on the modeling ...
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The delay of a circuit implemented in a Lookup table (LUT) based Field-Programmable Gate Arrays (FPGAs) is a combination of routing delays, and logic block delays. However most of an FPGA's area is devoted to prog...
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Bio-signal analysis is one of the most important approaches to biomedical engineering. The health information such as ECG, PCG, EMG and EEG are often recorded in digital format to be analyzed. In this paper, a bio-sig...
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Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional ...
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Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) integrated circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for resistance, capacitance and inductance of various TSV structures. Further, a reduced-order electrical circuit model is proposed for isolated TSVs as well as bundled structures for delay and SI analysis, and extracted TSV parasitics are employed in Spectre simulations for performance evaluations. Critical issues in the performance modeling for design space exploration of 3-D ICs such as cross-talk induced switching pattern dependent delay variation and cross-talk on noise are discussed. The error in these metrics when using the proposed models as compared to a field solver is contained to a few percentage points.
The clinical symptoms of metabolic disorders during neonatal period are often not apparent, if not treated early irreversible damages such as mental retardation may occur, even death. Therefore, practicing newborn scr...
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This work presents a study undertaken to characterise the FINISTERRAE supercomputer, one of the biggest NUMA systems in Europe. The main objective was to determine the performance effect of bus contention and cache co...
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This work presents a study undertaken to characterise the FINISTERRAE supercomputer, one of the biggest NUMA systems in Europe. The main objective was to determine the performance effect of bus contention and cache coherency as well as the suitability of porting strategies regarding irregular codes in such a complex architecture. Results show that: (1) cores which share a socket can be considered as independent processors in this context; (2) for big data sizes, the effect of sharing a bus degrades the final performance but masks the cache coherency effects; (3) the NUMA factor (remote to local memory latency ratio) is an important factor on irregular codes and (4) the default kernel allocation policy is not optimal in this system. These results allow us to understand the behaviour of thread-to-core mappings and memory allocation policies.
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