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IEEE International Conference on Cluster Computing, CLUSTER 2003

作者： Taboada, Guillermo L. Touriño, Juan Doallo, Ramón Computer Architecture Group Dep. of Electronics and Systems University of A Coruña Spain

ISBN: (纸本)0769520669

The use of Java for parallel programming on clusters according to the message-passing paradigm is an attractive choice. In this case, the overall application performance will largely dep.nd on the performance of the underlying Java message-passing library. This paper evaluates, models and compares the performance of MPI-like point-to-point and collective communication primitives from selected Java message-passing implementations on clusters with different interconnection networks. We have developed our own micro-benchmark suite to characterize the message-passing communication overhead and thus derive analytical latency models. © 2003 IEEE.

关键词： Parallel programming

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Efficient OpenCL-based concurrent tasks offloading on accelerators

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Procedia computer Science 2017年 108卷 2353-2357页

作者： A.J. Lázaro-Muñoz J.M. González-Linares J. Gómez-Luna N. Guil Dep. of Computer Architecture University of Malaga Spain Dep. of Computer Architecture and Electronics University of Córdoba Spain

Current heterogeneous platforms with CPUs and accelerators have the ability to launch several indep.ndent tasks simultaneously, in order to exploit concurrency among them. These tasks typically consist of data transfer commands and kernel computation commands. In this paper we develop a runtime approach to optimize the concurrency between data transfers and kernel computation commands in a multithreaded scenario where each CPU thread offloads tasks to the accelerator. It dep.oys a heuristic based on a temporal execution model for concurrent tasks. It is able to establish a near-optimal task execution order that significantly reduces the total execution time, including data transfers. Our approach has been evaluated employing five different benchmarks composed of dominant kernel and dominant transfer real tasks. In these experiments our heuristic achieves speedups up to 1.5x in AMD R9 and NVIDIA K20c accelerators and 1.3x in an Intel Xeon Phi (KNC) device.

关键词： OpenCL Command Queue Concurrency Tasks scheduling Commands Overlapping

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An inspector-executor algorithm for irregular assignment parallelization

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2004年 3358卷 4-15页

作者： Arenaz, Manuel Touriño, Juan Doallo, Ramón Computer Architecture Group Dep. Electronics and Systems University of A Coruña Spain

A loop with irregular assignment computations contains loop-carried output data dep.ndences that can only be detected at run-time. In this paper, a load-balanced method based on the inspector-executor model is proposed to parallelize this loop pattern. The basic idea lies in splitting the iteration space of the sequential loop into sets of conflict-free iterations that can be executed concurrently on different processors. As will be demonstrated, this method outperforms existing techniques. Irregular access patterns with different load-balancing and reusability properties are considered in the experiments. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Reusability

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Improving tasks throughput on accelerators using OpenCL command concurrency

arXiv

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arXiv 2018年

作者： Lázaro-Muñoz, A.J. González-Linares, J.M. Gómez-Luna, J. Guil, N. Dep. of Computer Architecture University of Málaga Spain Dep. of Computer Architecture and Electronics University of Córdoba Spain

A heterogeneous architecture composed by a host and an accelerator must frequently deal with situations where several indep.ndent tasks are available to be offloaded onto the accelerator. These tasks can be generated by concurrent applications executing in the host or, in case the host is a node of a computer cluster, by applications running on other cluster nodes that are willing to offload tasks in the accelerator connected to the host. In this work we show that a runtime scheduler that selects the best execution order of a group of tasks on the accelerator can significantly reduce the total execution time of the tasks and, consequently, increase the accelerator use. Our solution is based on a temporal execution model that is able to predict with high accuracy the execution time of a set of concurrent tasks launched on the accelerator. The execution model has been validated in AMD, NVIDIA, and Xeon Phi devices using synthetic benchmarks. Moreover, employing the temporal execution model, a heuristic is proposed which is able to establish a near-optimal tasks execution ordering that signicantly reduces the total execution time, including data transfers. The heuristic has been evaluated with five different benchmarks composed of dominant kernel and dominant transfer real tasks. Experiments indicate the heuristic is able to find always an ordering with a better execution time than the average of every possible execution order and, most times, it achieves a near-optimal ordering (very close to the execution time of the best execution order) with a negligible overhead. Concretely, our heuristic obtains, on average for all the devices, between 84% and 96% of the improvement achieved by the best execution order. Copyright © 2018, The Authors. All rights reserved.

关键词： computer architecture

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An inspector-executor algorithm for irregular assignment parallelization 04

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Proceedings of the Second international conference on Parallel and Distributed Processing and Applications

作者： Manuel Arenaz Juan Touriño Ramón Doallo Computer Architecture Group Dep. Electronics and Systems University of A Coruña Spain

ISBN: (纸本)9783540241287

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Basic study on the real-time three-dimensional position measurement of ground moving objects using an accelerometer and gyros 20

Basic study on the real-time three-dimensional position meas...

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20th ISPRS Congress Technical Commission V

作者： Okamoto, Yoshiwo Koizumi, Toshio Sirai, Yasuyuki Dep. Electrical Electronics and Computer Engineering Chiba Institute of Technology 2-17-1 Tsudanuma Narashino-shi Chiba275-0016 Japan Dep. Architecture and Civil Eng. Chiba Institute of Technology 2-17-1 Tsudanuma Narashino-shi Chiba275-0016 Japan Chiba Institute of Technology 2-17-1 Tsudanuma Narashino-shi Chiba275-0016 Japan

In recent years, electronics and computer technology have been applied to the development of survey instruments, and the methods of measurement have widely changed. We make use of sophisticated systems in daily base such as Total-Station, GPS and Laser-scanner, to name a few. However, a system based on light wave and/or radio wave has a weakness that it would not work if the waves were intercepted. An inertial survey system, on the other hand, functions indep.ndently of those waves, and it must be convenient under such circumstances. Therefore the authors are developing a portable and low-priced strap-down inertial navigation system. In this paper, the results from the field tests are presented, which have been performed on the equipment made on an experimental basis in order to investigate how the accuracy dep.nds on the measurement strategy, namely the nonstop or the stop-and-go strategy. © 2014 ISPRS. All Rights Reserved.

关键词： Surveys

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A mobile memory game for patients with Acquired Brain Damage: A preliminary usability study

A mobile memory game for patients with Acquired Brain Damage...

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IEEE EMBS International Conference on Information Technology Applications in Biomedicine (ITAB)

作者： M. J. Morón R. Yáñez D. Cascado C. Suárez-Mejías J. L. Sevillano Electronics Technology Dep. Universidad de Sevilla Sevilla Spain Computer Architecture and Technology Dep. Universidad de Sevilla Sevilla Spain UCAi Virgen del Rocio University Hospital Seville Spain

Memory rehabilitation and training is an important activity for patients with Acquired Brain Damage, including Cerebral Vascular Accident (stroke) and Traumatic Brain Injury patients. Although many interactive web-based and computer applications have been developed, the use of mobile devices apps has not been sufficiently studied from the point of view of its usability for these users. In this paper, a preliminary usability and accessibility study of a memory game for mobile devices (developed from scratch under Android OS) is presented. This study, based on the Shadow Expert Technique, allows improving the prototype and provides useful hints for increasing acceptability of Android applications, not only by Acquired Brain Damage patients but also by other people with cognitive disorders.

关键词： Games Usability Prototypes Androids Humanoid robots Training Diseases

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Electronic Energy System and Energy Management Algorithm for FutureHAUS

Electronic Energy System and Energy Management Algorithm for...

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IEEE Conference on Power electronics and Renewable Energy (CPERE)

作者： Vladimir Mitrovic Igor Cvetkovic Dushan Boroyevich Joseph Wheeler Robert Vance The Bradley Dep. of Electrical and Computer Engineering College of Engineering Center for Power Electronics Systems Virginia Polytechnic Institute and State University Blacksburg VA USA Center for Design Research School of Architecture + Design College of Architecture and Urban Studies Virginia Polytechnic Institute and State University Blacksburg VA USA

Technology advancements that happened in the last two decades have changed the way how people live, interact, and work more than any technology did in the past 100 years or so. Not only little “gadgets” enabled this enormous paradigm shift, the new innovative concepts have been well integrated into the design and manufacturing of computers, appliances, automobiles, airplanes, and ships, and it was about time to start seeing these concepts applied to the homes where building practices, by contrast, experienced a very slow, if not resistant effort to advance. At least they did before Virginia Tech demonstrated the use of advanced manufacturing concepts, prefabricated structures, and a great number of power electronics to redefine the conventional practice of modern home design. Its FutureHAUS won first place at the international competition in Dubai, UAE, validating an enormous societal desire to see this change finally happening. This paper will describe details of the electronic energy system implementation as well as an energy management algorithm developed to successfully achieve a net-positive energy balance in the FutureHAUS.

关键词： Resistance computers Renewable energy sources Home appliances Decision making Inverters Manufacturing

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SOC governed algorithm for an EV Cascaded H-Bridge connected to a DC charger

SOC governed algorithm for an EV Cascaded H-Bridge connected...

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European Conference on Power electronics and Applications

作者： Giulia Tresca Andrea Formentini Filippo Gemma Federico Lusardi Riccardo Leuzzi Pericle Zanchetta Electrical Computer and Biomedical Engineering Dept. University of Pavia Pavia Italy Telecommunications Engineering and Naval Architecture Dep. University of Genova Genova Italy MTA S. p. A (Power Electronics BU) Italy Electrical and Electronic Engineering Dept. University of Nottingham Nottingham United Kingdom

ISBN: (数字)9789075815399

ISBN: (纸本)9781665487009

Cascaded H-Bridge (CHB) converters have been considered valid candidates for replacing the two-level inverter in EV powertrain applications. This paper presents a State of Charge-governed algorithm for charging Li-Ion battery modules within a Cascaded H-Bridge converter for EV powertrain, connected to a DC charger. The novelty of this algorithm lies in the balanced and concurrent charge of the battery modules installed in all submodules of the three-phases, with no extra middle stage converter needed. Simulation and experimental results are shown to prove the validity of the novel architecture and the experimental setup is described.

关键词： Lithium-ion batteries Multilevel converters Voltage measurement Current measurement Process control Europe Mechanical power transmission

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