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Feedback-testing by using multiple input signature registers

Journal of Electronic Testing: Theory and Applications (JETTA) 1990年第3期1卷 213-213页

作者： Rudolph, M. Department of Automation of Circuit Design Computer Science Research Center at the University of Karlsruhe (FZI) Karlsruhe FRG

In this article, the use of Multiple Input Signature Registers (MISRs) as random pattern generators is investigated. This additional function helps to reduce hardware overhead and testing time, when BIST (Built-In Self-Test) structures are integrated on the chip, because the MISR can at the same time generate test patterns and collect test responses. A formula is presented, which determines the number of clock cycles needed to generate a given number of random patterns. Finally we suggest a method for how the number of test patterns can be reduced when the MISR acts as test pattern generator and compressor in a feedback loop.

关键词： Bult-in self-test design for testability MISR test-pattern generation testability analysis

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A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs

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IEEE Transactions on Electron Devices 2009年第8期56卷 1598-1607页

作者： Guo, Jyh-Chyurn Yeh, Chih-Ting Department of Electronics Engineering National Chiao Tung University Hsinchu 300 Taiwan Design Automation Technology Division Department of Circuit Design Industrial Technology Research Institute Hsinchu 31040 Taiwan

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance Cof dominates around 25% of the intrinsic gate capacitance (Cgint) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C of/Cgint above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design. © 2009 IEEE.

关键词： Nanotechnology

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An adaptive single event upset (SEU)-hardened flip-flop design

An adaptive single event upset (SEU)-hardened flip-flop desi...

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2019 IEEE International Conference on Electron Devices and Solid-State circuits, EDSSC 2019

作者： Zhang, Man Guo, Zhongjie Xu, WanCheng Department of Integrated Circuit Design Institute of Microelectronics Technology Xi'an China School of Automation and Information Engineering Xi'an University of Technology Xi'an China

ISBN: (纸本)9781728102863

In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering speed and reliability. The proposed structure makes itself more widely used in both space, defense applications and high-performance terrestrial applications. Spice simulation results show that the flip-flop has good performance of SEU-hardness and flexibility. © 2019 IEEE.

关键词： Radiation hardening

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High efficiency power management system for solar energy harvesting applications

High efficiency power management system for solar energy har...

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Asia-Pacific Conference on circuits and Systems

作者： Chang, Ming-Hung Wu, Jung-Yi Hsieh, Wei-Chih Lin, Shang-Yuan Liang, You-Wei Wei, Hwang Department of Electronics Engineering Institute of Electronics National Chiao Tung University Hsin-Chu 300 Taiwan Circuit Design Department Design Automation Technology Division Industrial Technology Research Institute Hsin-Chu 300 Taiwan

ISBN: (纸本)9781424474561

A high efficiency power management system for solar energy harvesting applications is proposed. The power management system receives power from photovoltaic (PV) cell and generate different voltage levels, they are 1V∼0.3V for analog circuitry and low power digital circuitry, -1.2V for super-cutoff technique in memory circuitry, and 10V for FLASH memory or I/O components. The great voltage varieties are suitable for green integrated regulator SoC electronics. The power management system also contains a rechargeable battery which is charged by multi-phase maximum power tracking (MPT) circuitry with the PV cell module. With the MPT circuitry, the power of PV cell can be regulated in the maximum power region. The average power efficiency of the MPT circuitry is up to 80%∼73%. All results are simulated in UMC 90nm bulk CMOS technology model. © 2010 IEEE.

关键词： Solar energy

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Optimized layout on ESD protection diode with low parasitic capacitance

Optimized layout on ESD protection diode with low parasitic ...

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology

作者： Yeh, Chih-Ting Ker, Ming-Dou Circuit Design Department Design Automation Technology Division Industrial Technology Research Institute Hsinchu Taiwan Institute of Electronics National Chiao-Tung University Hsinchu Taiwan Department of Electronic Engineering I-Shou University Kaohsiung Taiwan

ISBN: (纸本)9781424457984

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved. ©2010 IEEE.

关键词： CMOS integrated circuits

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Implementing a methodology for formally verifying RISC processors in HOL 6th

Implementing a methodology for formally verifying RISC proce...

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6th International Workshop on Higher Order Logic Theorem Proving and Its Applications, HUG 1993

作者： Tahar, Sofiène Kumar, Ramayya P.O. Box 6980 Karlsruhe76128 Germany Forschungszentrum Informatik Department of Automation in Circuit Design Haid-und-Neu Straße 10-14 Karlsruhe76131 Germany

ISBN: (纸本)9783540578260

In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction and successively prove the correctness between the neighbouring abstraction levels, so that the overall specification is correct with respect to its hardware implementation. The correctness proofs have been split into two steps so that the parallelism in the execution due to the pipelining of instructions, is accounted for. The first step shows that the instructions are correctly processed by the pipeline and the second step shows that the semantic of each instruction is correct. We have implemented the specification of the entire model and performed parts of the proofs in HOL. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Formal specification

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Implementational issues for verifying RISC-pipeline conflicts in HOL 7th

Implementational issues for verifying RISC-pipeline conflict...

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7th International workshop on Higher Order Logic Theorem Proving and its Applications, 1994

作者： Tahar, Sofiène Kumar, Ramayya University of Karlsruhe Institute of Computer Design and Fault Tolerance P.O. Box 6980 Karlsruhe76128 Germany Forschungszentrum Informatik Department of Automation in Circuit Design Haid-und-Neu StraBe 10-14 Karlsruhe76131 Germany

ISBN: (纸本)9783540584506

We outline a general methodology for the formal verification of instruction pipelines in RISC cores. The different kinds of conflicts, i. e. resource, data and control conflicts, that can occur due to the simultaneous execution of the instructions in the pipeline have been formally specified in HOL. Based on a hierarchical model for RISC processors, we have developed a constructive proof methodology, i.e. when conflicts at a specific abstraction level are detected, the conditions under which these occur are generated and explicitly output to the designer, thus easing their removal. All implemented specifications and tactics are kept general, so that the implementation could be used for a wide range of RISC cores. In this paper, the described formalization and proof strategies are illustrated via the DLX RISC processor. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Pipelines

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Test scheduling and controller synthesis in the CADDY-system

Test scheduling and controller synthesis in the CADDY-system

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European Conference on design automation

作者： M. Rudolph M. Neher W. Rosenstiel Department: Automation of Circuit Design Forschungszentrum Informatik an der Universitat Karlsruhe FZI Karlsruhe Germany

In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR.< >

关键词： circuit testing Automatic testing Control system synthesis Built-in self-test Automatic control circuit synthesis Hardware Scheduling algorithm Automatic generation control Signal synthesis

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The enhancement of power-rail ESD clamp circuit with gate-substrate-triggered technique

The enhancement of power-rail ESD clamp circuit with gate-su...

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International Symposium on Physical & Failure Analysis of Integrated circuits

作者： Chih-Ting Yeh Yung-Chih Liang Zhe-Wei Jiang Xin-Yuan Chang Circuit Design Department Design Automation Technology Division SoC Technology Center Industrial Technology and Research Institute Hsinchu Taiwan

In this work, the power-rail ESD clamp circuit fabricated in 130 nm CMOS process is investigated. In order to improve the ESD protection ability, the power-rail ESD clamp circuit with gate-substrate-triggered is proposed. By comparing with the other two techniques, gate-driven and substrate-triggered, it is shown that the secondary breakdown current of the power-rail ESD clamp circuit with gate-substrate-triggered is improved by 20%.

关键词： Electrostatic discharge Clamps MOS devices Protection CMOS technology circuit testing Stress Substrates Robustness Voltage

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Towards a methodology for the formal hierarchical verification of RISC processors

Towards a methodology for the formal hierarchical verificati...

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IEEE International Conference on Computer design: VLSI in Computers and Processors, (ICCD)

作者： S. Tahar R. Kumar Institute of Computer Design and Fault Tolerance University of Karlsruhe Karlsruhe Germany Department of Automation in Circuit Design Forschungszentrum Informatik Karlsruhe Germany

A general methodology, based on a hierarchical model of interpreters, is presented for formally verifying RISC cores. The abstraction levels used by a designer in the implementation of RISC cores, namely the instruction set level, the pipeline stage level, the phase level and the hardware implementation, are mirrored by this hierarchical model. The use of this model allows us to successively prove the correctness between two neighboring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into simplified steps. The first step shows that, under certain assumptions, no conflicts can occur between simultaneously executed instructions, and the second step shows that each instruction is implemented correctly by the sequential execution of its pipeline steps.< >

关键词： Reduced instruction set computing Microprocessors Pipeline processing Memory management Fault tolerance design automation circuit synthesis Hardware Logic Formal verification

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