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IEEE Annual Computing and Communication Workshop and Conference (CCWC)

作者： Umme Rani Irin Sajib Barua Md Minhajul Azmir Tasnuva Hassan Dewan Mohammed Circuit and System Design Department Ulkasemi Private Limited Dhaka Bangladesh

This paper gives an overview of SRAM design requirements and optimization methodologies for different threshold voltage devices. We look into how different SRAM read and write design options are impacted by the threshold voltage (V t ) changes brought on by process-voltage-temperature (PVT) variations. We investigated several approaches to achieve reliable threshold functioning. Additionally emphasized how different SRAM designs are impacted by process modifications. Here, nine different types of SRAM bit cells are analyzed for various threshold parameters to provide the optimal bit cell selection. Performance for read and write operations as well as power consumption are compared between these architectures. All simulations were performed using 12nm CMOS technology, and Cadence Tool was used to develop these designs. To reduce leakage current without compromising performance, it has been observed that higher-V t devices in cross-coupled latches and lower-V t devices in access transistors are favored. In terms of read and write performance as well as power consumption, this article analyzes the performance of nine different kinds of SRAM bit-cells.

关键词： Performance evaluation Semiconductor device modeling Latches Power demand Layout Random access memory CMOS technology

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design Process and Performance Analysis of Two Stage Differential Op-amp by Varying the Body Biasing in Fully Depleted Silicon on Insulator Technology 12

Design Process and Performance Analysis of Two Stage Differe...

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12th IEEE Annual Information Technology, Electronics and Mobile Communication Conference, IEMCON 2021

作者： Bappy, Md Maruf Abir Sarkar, Md Rubel Hasan, Saad Ibn Azmir, Md Minhajul Rashid, Dewan Mohammed Ulkasemi Private Limited Circuit and System Design Department Dhaka Bangladesh

ISBN: (纸本)9781665400664

The paper represents the full design process of a two-stage differential operational amplifier (op-amp) as well as a brief behavior analysis of the design. This work also demonstrates the performance variation of the op-amp by changing the potential level of the body biasing terminal in Fully Depleted Silicon on Insulator (FD-SOI) technology. If the FD-SOI technology is used, the performance of the circuit can be varied without changing the parameter of the CMOS (Complementary Metal Oxide Semiconductor) devices related to the physical dimensions (length and width). This paper showed the result of performance variation depending on different back bias connection and explains how FD-SOI technology provides the advantages to the designer in case of limited option of parameter variations. The supply voltage of the designed op-amp was 0.8V and the circuit simulations were done under room temperature, 27° Celsius using Cadence Spectre Analog design Environment (ADE). The result was varied without any manipulation of device parameter while only change was in bias potential. Due to the variation of bias potential the design performance is varied, the variation of gain is obtained from 34.15dB to 45.76dB, the bandwidth was varied from 3MHz to 7.18MHz at-3dB and leakage was also improved from 30.14µA to 26.02 µA. The phase margin was achieved up to 65.4° from 60.01°. To have a clear view of the performance a table is appended in this paper to demonstrate the advantage of FD-SOI technology in case of op-amp design. © 2021 IEEE.

关键词： Silicon on insulator technology

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VG-SOT MRAM design and Performance Analysis 12

VG-SOT MRAM Design and Performance Analysis

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12th IEEE Annual Information Technology, Electronics and Mobile Communication Conference, IEMCON 2021

作者： Sarkar, Md Rubel Bappy, Md Maruf Abir Azmir, Md Minhajul Rashid, Dewan Mohammed Hasan, Saad Ibn Ulkasemi Private Limited Circuit and System Design Department Dhaka Bangladesh

ISBN: (纸本)9781665400664

Voltage-Gated Spin-Orbit Torque (VG-SOT) Magnetic Tunneling Junction (MTJ) device has the aptitude for acquiring non-volatile memories (NVM), logic cells, neuromorphic circuits featuring low power, high-speed, and high-density. The characteristics of simultaneous field-free SOT switching and Voltage-Controlled Magnetic Anisotropy (VCMA) effect that modulates the barrier energy of the MTJ make it prominent among other MTJ devices. The VG-SOT MTJ device has separate read-write paths requiring two transistors and a diode per bit-cell to control read-write operation properly. This paper proposes a 2-Transistor, 1-Diode, 1-MTJ (2T1D1MTJ) VG-SOT Magnetic Random-Access Memory (MRAM) design. This design achieved an average write power of 10 µW, an average read power of 1.142 µW, and a read-write frequency of 250 MHz. In this design, a commercial 22 nm Fully Depleted Silicon on Insulator (FDSOI) Process design Kit (PDK), a physics-based VG-SOT MTJ device model developed by Spinlib, and Cadence Spectre simulator has been used to evaluate functionality and performance. © 2021 IEEE.

关键词： Spin Hall effect

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Climbing with Virtual Mentor by Means of Video-Based Motion Analysis

Climbing with Virtual Mentor by Means of Video-Based Motion ...

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3rd International Conference on Image Processing and Vision Engineering, IMPROVE 2023

作者： Richter, Julia Beltrán, Raul Beltrán Köstermeyer, Guido Heinkel, Ulrich Professorship Circuit and System Design Chemnitz University of Technology Reichenhainer Straße 70 Chemnitz Germany Department Sportwissenschaft und Sport Friedrich-Alexander-Universität Erlangen-Nürnberg Schlossplatz 4 Erlangen91054 Germany

ISBN: (纸本)9789897586422

Due to the growing popularity of climbing, research on non-invasive, camera-based motion analysis has received increasing attention. While extant work uses invasive technologies, such as wearables or modified walls and holds, or focusses on competitive sports, we for the first time propose a system that automatically detects motion errors that are typical for beginners with a low level of climbing experience by means of video analysis. In our work, we imitate a virtual mentor that provides an analysis directly after having climbed a route. We thereby employed an iPad Pro fourth generation with LiDAR to record climbing sequences, in which the climber’s skeleton is extracted using the Vision framework provided by Apple. We adapted an existing method to detect joints movements and introduced a finite state machine that represents the repetitive phases that occur in climbing. By means of the detected movements, the current phase can be determined. Based on the phase, single errors that are only relevant in specific phases are extracted from the video sequence and presented to the climber. Latest empirical tests with 14 probands demonstrated the working principle. We are currently collecting data of climbing beginners for a quantitative evaluation of the proposed system. © 2023 by SCITEPRESS – Science and Technology Publications, Lda.

关键词： Video analysis

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D-Band Demonstration of Quasi-Optical and Analogue Beam Reconfiguration using Phased Array and Lens for 6G Applications

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IEEE Transactions on Antennas and Propagation 2025年

作者： Campo, M. Arias Bruni, S. Lauer, A. Wleklinski, M. Gollor, U. Wischmann, W. Friedrich, A. Oikonomopoulos, C. Litschke, O. Herold, C. Malignaggi, A. Moroni, N. Krishnegowda, K. Carta, C. Keusgen, W. IMST GmbH Department of Antennas and EM Modeling Kamp-Lintfort47475 Germany IMST GmbH Department of HF-Circuits and System Integration Kamp-Lintfort47475 Germany IHP-Leibniz-Institut für innovative Mikroelektronik Department of Circuit Design Frankfurt15236 Germany Technische Universität Berlin Department of High Frequency Systems Berlin10587 Germany

In this paper, a hybrid quasi-optic and analogue beamforming approach is presented, involving an elliptical lens with an active focal plane array at D-band (110-170 GHz). Beamwidth reconfigurability and steering in two planes with enhanced performance are demonstrated. The quasi-optic technique minimizes the beam squint over frequency. Analogue phase shift in the focal plane array is used to increase the lens steering range. A prototype including two 4-channel D-band transceivers with on-chip antennas has been built as demonstrator. The resulting active focal plane array consists of 2x4 antenna elements, which are tuned in amplitude and phase to reconfigure the beam. The advantages of using a resonant leaky-wave cavity combined with a coherent array of feeds are discussed and quantified. Radiation pattern measurements performed with the calibrated active antenna validate the beam reconfiguration concept in two planes at 140 GHz. A steering loss reduction ranging from 2 to 4.5 dB is achieved in the whole D-band at 22° scan angle by applying beam steering in the feed radiation. © 1963-2012 IEEE.

关键词： Lens antennas

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BAG2 Assisted Hierarchical Analog Layout Synthesis for Planar Technologies

BAG2 Assisted Hierarchical Analog Layout Synthesis for Plana...

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Austrian Workshop on Microelectronics (Austrochip)

作者： Matthew Bio Wolfgang Scherr A. S. Agbemenu Santiago Martin Sondón Johannes Sturm Vinayak Hande Josef Ressel Centre for System-on-Chip Design Automation Carinthia Institute for Microelectronics Carinthia University of Applied Sciences Department of Computer Engineering Kwame Nkrumah University of Science and Technology Kumasi Ghana Department of Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continued to be developed targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley analog generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow as well as encourages design re-use due to using parameterized generators which can be scaled as required and this reduces the layout-development time compared to manual hand-made layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65nm and Cadence GPDK 45nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

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Synthetic gene circuits moving into the clinic

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Quantitative Biology 2021年第1期9卷 100-103页

作者： Shuguang Peng Huiya Huang Ping Wei Zhen Xie MOE Key Laboratory of Bioinformatics and Bioinformatics Division Center for Synthetic and System BiologyDepartment of AutomationBeijing National Research Center for Information Science and TechnologyTsinghua UniversityBeijing 100084China Beijing Syngentech Co. LtdZhongguancun Life Science ParkChangping DistrictBeijing 102206China Center for Gene Circuit and Cell Design Shenzhen Institute of Synthetic BiologyShenzhen Institutes of Advanced TechnologyChinese Academy of SciencesShenzhen 518055ChinaCenter for Quantitative BiologyAcademy for Advanced Interdisciplinary StudiesPeking UniversityBeijing 100871China

On November 28th 2020,SyngenTech,a China-based biotechnology company,announced that the company’s leading oncolytic virotherapeutic product,SynOVl.l,was approved for clinical trial by the *** and Drug *** synthetic bacterial or cell therapy[1,2],this is the first introduction of a viral therapy engineered using synthetic gene circuits into the *** with the clinical development of variable living therapeutics,we anticipate that synthetic gene circuits will receive increasing attention as a revolutionary technology to improve disease-treatment efficacy.

关键词： clinic clinical Together

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A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT design 22nd

A Write-Improved Half-Select-Free Low-Power 11T Subthreshold...

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22nd International Symposium on VLSI design and Test, VDAT 2018

作者： Sharma, Vishal Bisht, Pranshu Dalal, Abhishek Chouhan, Shailesh Singh Jattana, H.S. Vishvakarma, Santosh Kumar Nanoscale Devices VLSI Circuit and System Design Lab Electrical Engineering Indian Institute of Technology Indore IndoreM.P.453552 India EISLAB Department of Computer Science Electrical and Space Engineering Lulea University of Technology Lulea Sweden SCL Mohali Department of Space Govt. of India AjitgarhPunjab India

ISBN: (纸本)9789811359491

This work presents a new bit-interleaving low-power 11T subthreshold SRAM cell with the Data-Dependent Partial-Feedback Cutting to improve the write ability. The isolated read path of 11T enhances the read static noise margin (RSNM) which is equivalent to that of its hold SNM (HSNM), while the incorporated PMOS stacking in each of the inverter helps to reduce the leakage power of the cell. The half-select free behavior of the proposed 11T cell facilitates the bit-interleaving architecture of memory array that reduces the multi-bits error occurrence in a single word of data, and thus enhance the soft error tolerance. Using the proposed cell, a four-input FPGA lookup table (LUT) has been implemented working on 0.4V supply, which consumes 0.59 less leakage power as compared to that of 6T LUT. Finally, a two adjacent bits error correction technique is also suggested to incorporate with the proposed bit-interleaving 11T array, so that the effect of soft error can almost be neglected. It consumes comparable leakage and read access energy to that of one-bit error correcting conventional hamming code. © 2019, Springer Nature Singapore Pte Ltd.

关键词： Table lookup

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An Efficient Multi-fidelity Bayesian Optimization Approach for Analog circuit Synthesis

arXiv

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arXiv 2019年

作者： Zhang, Shuhan Lyu, Wenlong Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan Hu, Xiangdong State Key Lab of ASIC & System Microelectronics Department Fudan University China Shanghai High Performance Integrated Circuit Design Center China University of Texas at Dallas Dallas United States

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect. Copyright © 2019, The Authors. All rights reserved.

关键词： Timing circuits

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Corrigendum: "Analysis of hot carrier instability in a floating body cell" [Jpn. J. Appl. Phys. 63, 094002 (2024)]

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Japanese Journal of Applied Physics 2024年第11期63卷 119301-119301页

作者： Hiroomi Nakajima Tomoaki Shino Hironobu Furuhashi Jun Nishimura Tomoki Higashi Katsuyuki Fujita Kosuke Hatsuda Ryo Fukuda Takeshi Kajiyama Memory Development Strategy Group2 Memory Development Strategy Division KIOXIA Corporation 2-5-1 Kasama Sakae-ku Yokohama Kanagawa-Pref. 247-8585 Japan File Memory Device Peripheral Element Development Group File Memory Device Engineering Department KIOXIA Corporation 2-5-1 Kasama Sakae-ku Yokohama Kanagawa Pref. 247-8585 Japan Advanced Memory Development Center KIOXIA Corporation 800 Yamanoissiki-Cho Yokkaichi Mie-Pref. 510-0906 Japan Memory Device Engineering Department KIOXIA Systems Corporation 2-5-1 Kasama Sakae-ku Yokohama Kanagawa-Pref. 247-8585 Japan Circuit Technology Research Department AI & System Research Center Frontier Technology R&D Institute KIOXIA Corporation 2-5-1 Kasama Sakae-ku Yokohama Kanagawa Pref. 247-8585 Japan Memory Design Group 4 Memory Design Department 2 Memory Design Managing Department KIOXIA Corporation 2-5-1 Kasama Sakae-ku Yokohama Kanagawa Pref. 247-8585 Japan

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