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Expedient usage of wakeup receivers in wireless network applications: Wakeup vs cycle - How to compare those network concepts in the of power efficiency

Expedient usage of wakeup receivers in wireless network appl...

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9th International Workshop on Intelligent Solutions in Embedded systems, WISES 2011

作者： Paulo, Robert Johansson, Per Anders Kriesten, Daniel Heinkel, Ulrich Technical University Chemnitz Department of Circuit and System Design Chemnitz Germany

ISBN: (纸本)9783000334016

Wakeup concepts for wireless sensor networks are an upcoming field of interest for many applications. But when is it useful to attach a wakeup receiver or when shall approved mechanisms like duty cycle communication be used? In this paper a closer look on power consumption is taken to compare wakeup concept against duty cycle concept. © 2011 University of Applied Scien.

关键词： Wireless sensor networks

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10 GS/s 8-bit bipolar THA in SiGe technology

10 GS/s 8-bit bipolar THA in SiGe technology

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Norchip

作者： Yevgen Borokhovych J. Christoph Scheytt Chair of System Design IHP/BTU Joint Lab Frankfurt Germany Department of Circuit Design IHP Frankfurt Germany

design and measurement of the bipolar Track-and-Hold Amplifier is described in this paper. The circuit works at the sample rate of 10 GS/s and has linearity of 8-bit at input signal of 3 GHz. Based on the open-loop switched emitter follower architecture, the circuit implies several techniques to achieve 8-bit performance at GHz range. An input buffer and switch were modified to decrease errors and increase the speed.

关键词： Switches Fabrication

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Application of electromagnetic field simulation to 40Gbps optical receiver module development

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SEI Technical Review 2011年第72期 81-85页

作者： Uematsu, Yoshiaki Kinoshita, Tetsuro Kakue, Akihide Okayama, Akinori Sawada, Masahiko Itou, Makoto Sugimoto, Yoshiyuki Moriyama, Yutaka Takechi, Masaru Sawada, Sosaku Nakamura, Yuuichi Makino, Isamu Furusho, Masaru SimDesign TechnoCenter Sumitomo Electric System Solutions Co. Ltd. Japan Advanced Circuit Design R and D Department Transmission Device R and D Laboratories Japan Analysis Technology Research Center Japan

As the signal processing speed of electronic devices increases, transmission capability over 10Gbps has been required for printed wiring boards (PWBs).designing these PWBs capable of Giga-speed signal transmission, traditional MHz-based signal integrity simulation does not always ensure signal integrity.2008, Simdesign Technocenter, a business unite of Sumitomo Electric system Solution Co., Ltd., developed a new method to overcome this problem by combining 3-D electromagnetic simulation and several GHz signal integrity simulations. Since then, this method has enabled us to obtain accurate simulation results even for over 10 Gbps signals. In this study, this method is applied to 40Gbps optical receiver modules to optimize signal routing with the aim of improving transmission characteristics at over 10Gbps. Firstly, simulation results and measured values are compared to verify the conformity of simulation models. Next, simulation using a 40Gbps optical receiver module model is conducted to consider optimum signal routing. The result shows that this method reduces calculation time without compromising simulation accuracy, and thus increases simulation trial cycles. Although some differences are found between simulation results and actual measurements, similar transmission characteristics are obtained by changing model shapes and improving the modeling method of the adjacent area of a source injection point. Thus, we have succeeded in eliminating unnecessary design and trial routines by feeding back these simulation results to the actual PWB design process. This paper describes mainly challenges in the development of this design method using electromagnetic simulations and explains the advantages of the method.

关键词： Electromagnetic simulation

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Technology independent, embedded logic cores : Utilizing synthesizable embedded fpga-cores for asic design validation

Technology independent, embedded logic cores : Utilizing syn...

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5th International Workshop on Reconfigurable Communication-Centric systems on Chip 2010, ReCoSoC 2010

作者： Knäblein, Joachim Tischendorf, Claudia Markert, Erik Heinkel, Ulrich Department Circuit and System Design Chemnitz University of Technology Chemnitz Germany

ISBN: (纸本)9783866445154

This article describes an approach to embed technology independent, synthesizable FPGA-like cores into ASIC designs. The motivation for this concept is to combine the best aspects of the two chip design domains ASIC and FPGA. ASICs have better timing performance, are cheaper in mass production and less power consumptive. FPGAs have the big advantage to be reconfigurable. With FPGA-like cores being embedded into ASICs this extraordinary FPGA feature is transferred to the ASIC domain. The main innovative aspect of the approach proposed in this paper is not the concept of combining ASIC and FPGA on one die. This has already been done before. The novelty is to find ways to use standard components and cells for the FPGA part to be able to enhance ASIC designs without being restricted by technological and vendor related barriers. Among many other applications reconfigurability can be leveraged to improve verification problems, which arise with today's 100 million gate designs. Dedicated, synthesized PSL [23] monitors, which are loaded in embedded FPGA cores, accelerate the process of narrowing error locations on the chip.

关键词： Field programmable gate arrays (FPGA)

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High level synthesis using operation properties

High level synthesis using operation properties

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作者： Langer, Jan Heinkel, Ulrich Chemnitz University of Technology Department of Circuit and System Design Chemnitz 09126 Germany

ISBN: (纸本)9789048193035

We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval Language (ITL) and we assume the set of properties is complete, such that the properties alone are strong enough to map every possible sequence of input data to exactly one sequence of output data. A major advantage of using operation properties as a design method is the existence of commercial tools to check the completeness and consistency of the property set. Furthermore, operation properties are well suited for specifications of consecutive operations of finite length. We show the practicality of our method by implementing a particle filter for a localization application. © 2010 Springer Science+Business Media B.V.

关键词： High level synthesis

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Power optimization for VLSI circuits and systems

Power optimization for VLSI circuits and systems

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology

作者： Zhao, Peiyi Wang, Zhongfeng Hang, Guoqiang Integrated Circuit Design and Embedded System Lab. School of Computational Science Chapman University Orange CA 92604 United States Information and Electronic Engineering Department Zhejiang University Hangzhou China Broadcom Corp. Irvine CA United States

ISBN: (纸本)9781424457984

Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture level. ©2010 IEEE.

关键词： VLSI circuits

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Power Optimization for VLSI circuits and systems

Power Optimization for VLSI Circuits and Systems

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Peiyi Zhao Zhongfeng Wang Guoqiang Hang Integrated Circuit Design and Embedded System Lab School of Computational Science Chapman University Orange CA USA Broadcom Corporation Irvine CA USA Information and Electronic Engineering Department University of Zhejiang Hangzhou China

关键词： low power VLSI clocking system flip-flop

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Low power design of VLSI circuits and systems

Low power design of VLSI circuits and systems

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2009 8th IEEE International Conference on ASIC, ASICON 2009

作者： Zhao, Peiyi Wang, Zhongfeng Integrated Circuit Design and Embedded System Lab. Math and Computer Science Department Chapman University Orange CA 92604 United States Broadcom Corp. Irvine CA United States

ISBN: (纸本)9781424438686

Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. ©2009 IEEE.

关键词： Flip flop circuits

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4-bit, 16 GS/s ADC with new parallel reference network

4-bit, 16 GS/s ADC with new parallel reference network

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IEEE International Conference on Microwaves, Communications, Antennas and Electronic systems, COMCAS

作者： Yevgen Borokhovych Hans Gustat Christoph Scheytt System Design IHP BTU Joint Laboratory Frankfurt Germany Department of Circuit Design IHP Frankfurt Germany

This paper presents a high-speed 4 bit full-flash analog-to-digital converter with a new parallel reference network for an UWB radar. The ADC is implemented in 190 GHz SiGe BiCMOS technology, has more than 6 GHz effective resolution input bandwidth and operates up to 16 GSample/s. Power dissipation is 1.15 W including test buffers and 750 mW of the converter itself.

关键词： Bandwidth Ultra wideband radar Resistors Tail Parasitic capacitance Frequency Radar applications circuit synthesis Food industry Immune system

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Ultra low power flash ADC for UWB transceiver applications

Ultra low power flash ADC for UWB transceiver applications

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European Conference on circuit Theory and design, ECCTD

作者： Mohammad Masoumi Erik Markert Ulrich Heinkel Georges Gielen Circuit and System Design Technische Universitat Chemnitz-Zwickau Chemnitz Germany Department of Electrical Engineering Katholieke Universiteit Leuven Leuven Belgium

In this paper a low power, 4-bit, 50 MHz flash ADC in 130 nm technology is presented. Power consumption is the most important objective in this ADC. Two blocks, S/H and Latch, can be omitted in this ADC because of the comparator and encoder structures. Flash ADC has a peak SNDR of 23.47 dB at Nyquist frequency while the power consumption is 130 muW with a binary code encoder. This reduces to 115 muW if output data are in Gray code. The proposed ADC achieves 0.1625 pJ per conversion-step if the output is binary.

关键词： Transceivers Voltage Energy consumption Resistors Capacitance Latches circuit noise Frequency Charge transfer Feedback circuits

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