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Ultra low power flash ADC for UWB transceiver applications

Ultra low power flash ADC for UWB transceiver applications

引用

European Conference on circuit Theory and design, ECCTD

作者： Mohammad Masoumi Erik Markert Ulrich Heinkel Georges Gielen Circuit and System Design Technische Universitat Chemnitz-Zwickau Chemnitz Germany Department of Electrical Engineering Katholieke Universiteit Leuven Leuven Belgium

In this paper a low power, 4-bit, 50 MHz flash ADC in 130 nm technology is presented. Power consumption is the most important objective in this ADC. Two blocks, S/H and Latch, can be omitted in this ADC because of the comparator and encoder structures. Flash ADC has a peak SNDR of 23.47 dB at Nyquist frequency while the power consumption is 130 muW with a binary code encoder. This reduces to 115 muW if output data are in Gray code. The proposed ADC achieves 0.1625 pJ per conversion-step if the output is binary.

关键词： Transceivers Voltage Energy consumption Resistors Capacitance Latches circuit noise Frequency Charge transfer Feedback circuits

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Low power design of vlsi circuits and systems

Low power design of vlsi circuits and systems

引用

International Conference on ASIC

作者： Peiyi Zhao Zhongfeng Wang Integrated Circuit Design and Embedded System Lab Math and Computer Science Department Chapman University Orange CA USA Broadcom Corporation Irvine CA USA

Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.

关键词： Very large scale integration circuits and systems Clocks Energy consumption design optimization Frequency Power dissipation system performance Flip-flops Latches

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4-bit, 15 GS/s ADC in SiGe

4-bit, 15 GS/s ADC in SiGe

引用

Norchip

作者： Yevgen Borokhovych Hans Gustat Chair of System Design IHP BTU Joint Laboratory Frankfurt Germany Department of Circuit Design IHP Frankfurt Germany

This paper presents a high-speed 4 bits full-flash Analog-to-Digital Converter for an UWB radar applications, implemented in 190 GHz SiGe BiCMOS technology. The ADC occupies 1.5 × 1.5 mm 2 , including bondpads. Converter has 6 GHz input bandwidth and operates up to 15 GSample/s. Power dissipation is 1 W including test buffers and 600 mW for a core part itself.

关键词： Silicon germanium Germanium silicon alloys Ultra wideband radar Frequency Clocks Radar signal processing Jitter Power dissipation Radar applications Radar tracking

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EKV3 parameter extraction and characterization of 90nm RF-CMOS technology

EKV3 parameter extraction and characterization of 90nm RF-CM...

引用

14th International Conference on Mixed design of Integrated circuits and systems

作者： Yoshitomi, S. Bazigos, A. Bucher, M. Toshiba Corp. Semiconductor Company Japan National Technical University of Athens Greece Technical University of Crete Greece Department of System-LSI Toshiba Corp. Semiconductor Company Saiwai-Ku Kawasaki 212-8583 1 Komukai Toshiba-Cho Japan Department of EE and CS Microelectronic Circuit Design Group National Technical University of Athens 157 73 Zographou Athens Heroon Polytechniou 9 Greece Dept. of Electronic and Computer Engineering Technical University of Crete 73100 Chania Crete Greece

ISBN: (纸本)9788392263241

EKV3 is a circuit-design-oriented compact MOSFET model for analog/RF IC design. The paper presents parameter extraction guidelines and modelling using EKV3 for TOSHIBA's 90nm RF-CMOS technology covering DC, CV and RF (S-parameter) and temperature scalability. RF verification was done by the use of multi-finger MOSFETs with many variations of gate length, width of unit fingers and number of fingers. A scalable RF model was successfully created. Extraction of RF parasitics and their scaling with RF layout is investigated. The EKV3 model successfully predicted high-frequency behaviour of 90nm CMOS up to 20GHz over a wide range of bias conditions.

关键词： EKV3 model compact modelling RF CMOS RF parasitics parameter extraction scaling

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The Impact Of Technology Parameters On The Performance Of Common-gate LNAs

The Impact Of Technology Parameters On The Performance Of Co...

引用

International Conference on Mixed design of Integrated circuits and systems (MIXDES)

作者： T. Stucke N. Christoffers R. Kokozinski S. Kolnsberg B.J. Hosticka Department of Circuit Design and Wireless Systems SDS Fraunhofer Institute of Microelectronic Circuits and System Duisburg Germany Department Signal Processing and System Design SYS the same Institute Germany

In this paper the impact of short channel effects on the performance of common-gate LNAs (CG-LNAs) is presented. It based on the modeling the MOSFET behavior including its intrinsic and extrinsic parasitics in all possible regions of operation. Characteristic performance figures of the used CMOS technology are defined and the bias dependent minimum input reflection coefficient and noise figure is determined. The paper shows furthermore the advantage of biasing the CG-LNA in the moderate inversion region

关键词： MOSFET circuits Noise figure CMOS technology Acoustic reflection Capacitors Transconductance Microelectronics Linearity Inductors Frequency

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Organization of a microprocessor design process using Internet-based interoperable workflows

引用

3rd International Symposium on Quality Electronic design, ISQED 2002

作者： Trung, Nguyen Quang Kokoszka, A. Siekierska, K. Pawlak, A. Obrebski, D. Lugowski, N. Department of Integrated Circuit and System Design Institute of Electron Technology Poland

ISBN: (纸本)0769515614

The paper presents a new approach towards large system design in distributed teams based on a workflow technology. The techniques applied introduce interoperability among design tools across computing platforms and organization borders. They result in an improved quality of wide area engineering collaboration. After a short discussion about selected aspects of the applied workflow technology from an electronic design engineers' perspective, an Internet-based distributed design process of IP components with emphasis on specific elements of microprocessor designs is introduced. As an example, we present a workflow that enables integration and interoperability of selected IP design tasks, represented as parallel and serial sets of the workflow activities. The workflows that were employed in the design process had been developed for the purpose of design task integration in the pan-European project E-Colleg. They can be effectively adopted by distributed teams working on multiple sites, multiple platforms for remote project management. © 2002 IEEE.

关键词： Interoperability

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Organization of a microprocessor design process using Internet-based interoperable workflows

引用

IEEE International Symposium on Quality Electronic design

作者： Nguyen Quang Trung A. Kokoszka K. Siekierska A. Pawlak D. Obrebski N. Lugowski Department of Integrated Circuit and System Design Institute for Electron Technology Poland

ISBN: (纸本)0769515614

关键词： Microprocessors Process design Internet Decision support systems Economic indicators

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High dynamic range CMOS image sensor with conditional reset

High dynamic range CMOS image sensor with conditional reset

引用

Custom Integrated circuits Conference (CICC)

作者： Sung-Hyun Yang Kyoung-Rok Cho Communication Circuit & System Design Laboratory Department of Computer and Communication Engineering Chungbuk National University Cheonghu Chungbuk South Korea

In this paper, we propose a new image pixel structure for high dynamic range operation, which is based on a multiple sampling scheme and conditional reset circuits. To expand the dynamic range of the sensor, the output of the pixel is sampled multiple times in an integration time. In each sampling, the output of the pixel is compared with a reference voltage, and the result of this comparison activates the conditional reset circuit. The times of conditional reset during the integration contribute to the increase of the dynamic range of the sensor. Dynamic range can be increased to N, where N is the sampling times in an integration time. The test chip was fabricated with a 0.65-/spl mu/m CMOS technology (2-P, 2-M).

关键词： Dynamic range CMOS image sensors Voltage Signal to noise ratio Image sensors circuits Image sampling Pixel CMOS technology Image quality

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Soft core based model of a microcomputer family 2

Soft core based model of a microcomputer family

引用

2nd IEEE International Symposium on Quality Electronic design, ISQED 2001

作者： Trung, Nguyen Quang Siekierska, Krystyna Department of Integrated Circuit and System Design Institute of Electron Technology Poland

ISBN: (纸本)0769510256

A significant trend towards developing soft core based designs has been observed for the last few years. The emphasis is on reduction of time to market and bridging the growing gap between technology capacity and design productivity. The paper briefly presents the design of a configurable microcomputer family model based on a VHDL soft core. Modeling process with emphasis on coding style is mentioned. The paper also proposes a virtual component configuration tool that gives the core user an effective way to set up the model of the microcomputer family upon the need of particular end users, and introduces the implementation of industrial microcomputer series based on the model. The work on the extension of the soft core with regard to its reusability, as well as on the development of a configurable model of microcontroller class based on the soft core is being done. © 2001 IEEE.

关键词： Reusability

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Soft core based model of a microcomputer family

Soft core based model of a microcomputer family

引用

IEEE International Symposium on Quality Electronic design

作者： Nguyen Quang Trung K. Siekierska Department of Integrated Circuit and System Design Institute for Electron Technology Poland

ISBN: (纸本)0769510256

A significant trend towards developing soft core based designs has been observed for the last few years. The emphasis is on reduction of time to market and bridging the growing gap between technology capacity and design productivity. The paper briefly presents the design of a configurable microcomputer family model based on a VHDL soft core. Modeling process with emphasis on coding style is mentioned. The paper also proposes a virtual component configuration tool that gives the core user an effective way to set up the model of the microcomputer series, upon the need of particular end-users, and introduces the implementation of industrial microcomputer series based on the model. The work on the extension of the soft core with regard to its reusability as well as on the development of a configurable model of microcontroller class based on the soft core is being done.

关键词： Microcomputers Registers Integrated circuit technology design methodology Guidelines Electrons Time to market Productivity Manufacturing industries Microcontrollers

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