检索结果-内蒙古大学图书馆

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Karthikeyan Sankaralingam S.W. Keckler W.R. Mark D. Burger Computer Architecture and Technology Laboratory Department of Computer Sciences University of Texas Austin USA

ISBN: (纸本)9780769520438

Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper presents a classification scheme for data-parallel program attributes, and proposes micro-architectural mechanisms to support applications with diverse behavior for using a single reconfigurable architecture. We focus on the following four broad kinds of data-parallel programs - DSP/multimedia, scientific, networking, and real-time graphics workloads. While all of these programs exhibit high computational intensity, coarse-grain regular control behavior, and some regular memory access behavior, they show wide variance in the computation requirements, fine grain control behavior, and the frequency of other types of memory accesses. Based on this study of application attributes, this paper proposes a set of general micro-architectural mechanisms that enable a baseline architecture to be dynamically tailored to the demands of a particular application. These mechanisms provide efficient execution across a spectrum of data-parallel application and can be applied to diverse architectures ranging from vector cores to conventional superscalar cores. Our results using a baseline TRIPS processor show that the configurability of the architecture to the application demands provides harmonic mean performance improvement of 5%-55% over scalable yet less flexible architectures, and performs competitively against specialized architectures.

关键词： computer architecture Graphics Hardware Application software Computational modeling Communication system control Digital signal processing chips Engines Laboratories Reconfigurable architectures

来源：评论

学校读者我要写书评

暂无评论

Scalable hardware memory disambiguation for high ILP processors 36

Scalable hardware memory disambiguation for high ILP process...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： S. Sethumadhavan R. Desikan D. Burger C.R. Moore S.W. Keckler Department of Computer Sciences Computer Architecture and Technology Laboratory Department of Electrical and Computer Engineering University of Texas Austin USA

ISBN: (纸本)9780769520438

This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows with issue width and pipeline depth, the load/store queues (LSQ) threaten to become a bottleneck in both power and latency. By employing lightweight approximate hashing in hardware with structures called Bloom filters, many improvements to the LSQ are possible. We propose two types of filtering schemes using Bloom filters: search filtering, which uses hashing to reduce both the number of lookups to the LSQ and the number of entries that must be searched, and state filtering, in which the number of entries kept in the LSQs is reduced by coupling address predictors and Bloom filters, permitting smaller queues. We evaluate these techniques for LSQs indexed by both instruction age and the instruction's effective address, and for both centralized and physically partitioned LSQs. We show that search filtering avoids up to 98% of the associative LSQ searches, providing significant power savings and keeping LSQ searches to under one high-frequency clock cycle. We also show that with state filtering, the load queue can be eliminated altogether with only minor reductions n performance for small instruction window machines.

关键词： Hardware Filtering Filters Delay Scalability Pipelines Out of order computer architecture Laboratories Clocks

来源：评论

学校读者我要写书评

暂无评论

Microprocessor pipeline energy analysis 03

Microprocessor pipeline energy analysis

引用

International Symposium on Low Power Electronics and Design (ISLPED)

作者： K. Natarajan H. Hanson S.W. Keckler C.R. Moore D. Burger Department of Electrical and Computer Engineering University of Texas Austin USA Department of Computer Sciences Computer Architecture and Technology Laboratory USA

ISBN: (纸本)9781581136821

The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wide-issue, highly speculative cores. Microarchitectural speculation, such as branch prediction, increases instruction throughput but carries a power burden due to wasted power for mis-speculated instructions. Pipeline over-provisioning supplies excess resources which often go unused. In this paper, we use our detailed performance and power model for an Alpha 21264 to measure both the useful energy and the wasted effort due to mis-speculation and over-provisioning. Our experiments show that flushed instructions account for approximately 6% of total energy, while over-provisioning imposes a tax of 17% on average. These results suggest opportunities for power savings and energy efficiency throughout microprocessor pipelines.

关键词： Microprocessors Pipelines Microarchitecture Circuits Energy measurement Power measurement Energy consumption Clocks Permission Hardware

来源：评论

学校读者我要写书评

暂无评论

A reconfigurable monitoring system for large-scale network computing

A reconfigurable monitoring system for large-scale network c...

引用

9th International Euro-Par Conference on Parallel Processing, Euro-Par 2003

作者： Subramanyan, Rajesh Miguel-Alonso, José Fortes, José A.B School of Electrical and Computer Engineering Purdue University West LafayetteIN47907 United States Department of Computer Architecture and Technology The University of the Basque Country UPV/EHU San Sebastian Spain Department of Electrical and Computer Engineering University of Florida GainesvilleFL32611 United States

ISBN: (纸本)354040788X

The dynamic nature of large-size Network Computing Systems (NCSs) and the varying monitoring demands from the end-users pose serious challenges for monitoring systems (MSs). A statically configured MS initially adjusted to perform optimally may end performing poorly. A reconfiguration mechanism for a distributed MS is proposed. It enables the MS to react to changes in the available resources, operating conditions, and monitoring requirements, while maintaining high performance and low monitoring overheads. A localized decision process involving two adjacent intermediate-level managers (ILMs) and values of a local node performance parameter called temperature together determine transformations (merge, split, migrate) for each ILM. The reconfiguration mechanisms are derived reusing SNMP primitives. Interactions between MS and NCS are studied by defining a queuing model, and by evaluating different configuration schemes using simulation. Results for the static and reconfigurable schemes indicate that reconfiguration improves performance in terms of lower processing delays at the ILMs. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Monitoring

来源：评论

学校读者我要写书评

暂无评论

Parallel single front genetic algorithm: performance analysis in a cluster system

Parallel single front genetic algorithm: performance analysi...

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： F. De Toro J. Ortega B. Paechter Electronic and Computer Science Department University of Huelva Spain Computer Architecture and Technology Department University of Granada Spain Computer Science Department Napier University UK

In this paper a performance analysis in a cluster system of the parallel single front genetic algorithm (PSFGA) is carried out. The PSFGA is a parallel evolutionary optimizer for multiobjective problems that use a structured population in the form of a set of islands. The SFGA, an elitist evolutionary algorithm with a clearing procedure that uses a grid in the objective space for diversity maintaining purposes, is performed on each subpopulation (island) associated to a different area in the search space. Experimental results show that PSFGA outperforms SFGA and SPEA (strength Pareto evolutionary algorithm) in the cases studied.

关键词： Genetic algorithms Performance analysis Evolutionary computation Constraint optimization computer science computer architecture Dissolved gas analysis Art Distributed processing

来源：评论

学校读者我要写书评

暂无评论

Learning semi naïve bayes structures by estimation of distribution algorithms

Lecture Notes in Computer Science (including subseries Lectu...

引用

Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2003年 2902卷 224-258页

作者： Robles, V. Larrañaga, P. Peña, J.M. Pérez, M.S. Menasalvas, E. Herves, V. Department of Computer Architecture and Technology Technical University of Madrid Madrid Spain Department of Computer Science and Artificial Intelligence University of the Basque Country San Sebastián Spain

Recent work in supervised learning has shown that a surprisingly simple Bayesian classifier called naïve Bayes is competitive with state of the art classifiers. This simple approach stands from assumptions of conditional independence among features given the class. Improvements in accuracy of naïve Bayes has been demonstrated by a number of approaches, collectively named semi naïve Bayes classifiers. Semi naïve Bayes classifiers are usually based on the search of specific values or structures. The learning process of these classifiers is usually based on greedy search algorithms. In this paper we propose to learn these semi naïve Bayes structures through estimation of distribution algorithms, which are non-deterministic, stochastic heuristic search strategies. Experimental tests have been done with 21 data sets from the UCI repository. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Heuristic algorithms

来源：评论

学校读者我要写书评

暂无评论

On-line adaptive fuzzy controller: application of helicopter stabilization of the altitude of a helicopter

On-line adaptive fuzzy controller: application of helicopter...

引用

IEEE International Conference on Computational Intelligence for Measurement Systems and Applications (CIMSA)

作者： I. Rojas H. Pomares C.G. Puntonet F. Rojas M. Rodriguez O. Valenzuela Department of Architecture and Computer Technology University of Granada Spain Department of Applied Mathematics University of Granada Spain

When confronted with a control problem for a complicated physical process, a control engineer generally follows a relatively systematic design procedure. In this paper we design an on-line controller which is able to modify and adapt the rule base of the system with just only qualitative knowledge about the plant to be controlled. In our example, the system is an helicopter, and the objective is to control the altitude of the helicopter, when the mass of the system change, or other parameters defining the helicopter has been modified.

关键词： Helicopters Programmable control Adaptive control Fuzzy control Control systems Fuzzy systems Weight control Fuzzy sets Adaptive systems Process control

来源：评论

学校读者我要写书评

暂无评论

A combined interval and floating-point comparator

A combined interval and floating-point comparator

引用

Asilomar Conference on Signals, Systems & computers

作者： C.M. Kaas J.E. Stine VLSI Computer Architecture Arithmetic and CAD Research Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are often too slow for numerically intensive calculations. This paper presents the design of a comparator that performs either interval or two's complement/floating-point comparisons. This comparator requires only slightly more area than a conventional floating point comparator, and provides a significant performance improvement over software implementations of interval comparisons. Both serial and parallel designs are examined and the results are implemented in AMI 0.60 /spl mu/m technology.

关键词： Hardware Digital arithmetic Very large scale integration Error correction Upper bound Coprocessors Delay estimation computer architecture Laboratories computerized monitoring

来源：评论

学校读者我要写书评

暂无评论

Variations on truncated multiplication

Variations on truncated multiplication

引用

Euromicro Symposium on Digital System Design

作者： J.E. Stine O.M. Duverne VLSI Computer Architecture Arithmetic and CAD Research Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

Truncated multiplication can be used to significantly reduce the power dissipation for applications that do not require correctly-rounded results. This paper presents an efficient method for truncated multiplication called hybrid-correction truncation that utilizes the advantages of two previous methods to obtain lower average and maximum absolute error. Comparisons are presented contrasting power, area, and delay for all three methods compared to standard parallel multipliers. Estimates indicate that hybrid truncated multipliers dissipate slightly less power and consume slightly less area than previous methods for truncated multiplication. In addition, utilization of the hybrid truncation method can provide a method for altering the implementation within certain limits to meet a given precision.

关键词： Power dissipation Digital signal processing Delay Hardware Very large scale integration computer architecture Digital arithmetic Laboratories Application software Clocks

来源：评论

学校读者我要写书评

暂无评论

A hierarchical fuzzy steering controller for mobile robots

A hierarchical fuzzy steering controller for mobile robots

引用

IEEE International Conference on Computational Intelligence for Measurement Systems and Applications (CIMSA)

作者： M. Teiner I. Rojas K. Goser O. Valenzuela Department of Electrical Engineering-Microelectronics University of Dortmund Germany Department of Computer Architecture and Computer Technology University of Granada Spain Department of Applied Mathemataic University of Granada Spain

This paper describes a hierarchical fuzzy steering controller approach to local navigation of an autonomous sensor equipped mobile robots. Two goals are considered simultaneously: obstacle avoidance, so that the robot is piloted safely in an unknown environment; and reaching an target point. A two-step approach to build a fuzzy system is presented. In the first stage signals are processed by conventional methods to get an output vector indicating the direction and the closeness of obstacles around. Stage two is a basic task steering controller, that is based on fuzzy logic. The modular structure of the first stage allows modifications on the robot. So there is no need for a redesign of the controller's architecture, when the controller is used in different applications. Adaptation to a new task is done simply by adjusting the controller to other conditions. Then the robustness of this controller is demonstrated in simulations by means of erroneous signals of the sensor modules. Finally the controller is used in combination with another basic task controller for 'Reaching an Aiming Point'. In a higher level a controller ascertains priority of the controllers and manages the resulting steering commands.

关键词： Fuzzy control Robot control Mobile robots Navigation Sensor phenomena and characterization Robot sensing systems Fuzzy systems Signal processing Fuzzy logic Robust control

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：