A multistatic FMCW radar system is being developed to serve as an obstacle warning and 2D/3D- location sensor on autonomous vehicles. In this paper the additional use of available phase data is considered and some rec...
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A multistatic FMCW radar system is being developed to serve as an obstacle warning and 2D/3D- location sensor on autonomous vehicles. In this paper the additional use of available phase data is considered and some recently obtained experimental results are introduced.
Standard user-level networking architecture such as Virtual Interface (VI) architecture enables distributed applications to perform low overhead communication over System Area Networks (SANs). This paper describes how...
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The Hybrid technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor proce...
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The Hybrid technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor processors, semiconductor memories with built-in processors, high-speed optical interconnects, and high-density holographic storage. While there are major challenges in all aspects of this project, those in processor architecture are the focus of this paper. Fundamental differences between RSFQ circuits and conventional semiconductor circuits, including a radical jump in clock speed, make today's processor design approaches inappropriate for HTMT. Sequential instruction dispatching, even within the lowest programming unit (a strand), will lead to unacceptably high latencies, hence poor performance. We propose alternative processor designs which use fine-grain synchronizations between individual instructions in order to avoid these bottlenecks.
A two-port memory contains two similar ports, which can be accessed separately and independent of each other. In this paper, logical fault models are derived for the effect of shorts between the ports. The result is a...
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A two-port memory contains two similar ports, which can be accessed separately and independent of each other. In this paper, logical fault models are derived for the effect of shorts between the ports. The result is a set of new fault models, based on circuit simulation, together with a new test.
This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress...
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This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.
Field-programmable logic (FPL) densities and performance have steadily improved, allowing DSP solutions to be integrated on a single FPL chip. The primary limitation of FPLs, in DSP-centric applications, is their intr...
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Field-programmable logic (FPL) densities and performance have steadily improved, allowing DSP solutions to be integrated on a single FPL chip. The primary limitation of FPLs, in DSP-centric applications, is their intrinsically weak arithmetic performance compared to DSP microprocessors and ASICs. In some cases, distributed arithmetic (DA) has been used to mask FPL arithmetic inadequacies. The Residue Number System (RNS) has demonstrated an ability to support high-bandwidth arithmetic with limited resources. This paper presents a methodology for merging distributed arithmetic with the residue number systems to achieve high-performance FPL solutions.
The high volume of information available on the Internet makes it necessary to use search and organization tools to filter and display it. This presentation must make efficient use of the surface the browser leaves;th...
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ISBN:
(纸本)3540650784
The high volume of information available on the Internet makes it necessary to use search and organization tools to filter and display it. This presentation must make efficient use of the surface the browser leaves;this is even more true in the case of personalized newspapers, in which all the news and publicity must be presented in only one "coup d'oeil", to make them as effective as possible. In this paper, a system to automatically paginate web newspapers on the browser is presented. The system uses a genetic algorithm with integer representation and variable mutation amplitude, fine-tuned by a greedy algorithm. This combination proves to be much better than the genetic algorithm alone. The algorithm is proved to be able to lay out the web page in real time, that is, a time insignificant with respect to the time it takes to load an average page. The system will be embedded in several personalized news sites that are being developed at Granada University.
This paper presents a self-organizing approach for mobile robot path planning problems in dynamic environments by using case-based reasoning together with a more conventional method of grid-map based path planning. Th...
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NASA's Mission to Planet Earth (MTPE) is planning to launch the Earth Observing System (EOS) starting in 1998. The large number of planned remote sensing satellites will bring 500 Gigabytes of information per day....
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