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Proceedings of the 24th International Symposium on Microarchitecture - MICRO 24

作者： Hoogerbrugge, Jan Corporaal, Henk Mulder, Hans Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems

ISBN: (纸本)0897914600

This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code scheduling possibilities which are not available in traditional operation-triggered architectures. In addition the scheduling freedom is extended by the use of so-called hybridpipelined function utits. In order to exploit this tleedom, existing scheduling techniques need to be extended. We present a software pipelirtirtg technique, based on Lam's algorithm, which exploits the potential of !mnsport-triggered architectures. Performance results are presented for several benchmak loops. Depending on the available transport capacity, MFLOP rates may increase significantly as compared to scheduling without the extra degrees of freedom. © 1991 ACM.

关键词： Scheduling

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An implementation of a barotropic numerical weather prediction model in the functional language SISAL 90

An implementation of a barotropic numerical weather predicti...

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2nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 1990

作者： Chang, Pau S. Egan, Gregory K. Jt. Roy. Melbourne Inst. of Technol. and Cmw. Scientific and Industrial Research Organisation Parallel Systems Architecture Project Australia Royal Melbourne Institute of Technology Dept of Communication and Electrical Engineering 124 La Trobe St. Melbourne3000 Australia Department of Computer Systems Engineering Swinburne Institute of Technology School of Electrical Engineering John Street Hawthorn3122 Australia

ISBN: (纸本)0897913507

Numerical Weather Prediction (NWP) is acknowledged as being of vital importance to economy. The demand that NWP places on computing system performance has increased dramatically since the introduction of computer systems and is siili growing. This paper describes the implementation of a one-level barotropic spectral NWP model using the high level functional language SISAL. Our initial approach was a direct transliteration from FORTRAN to SISAL, the result of which was a large amount of array copying and loss of parallelism. The algorithm of the model was then rearranged to enable effective exploitation of parallelism by an optimising SISAL compiler. The parallel implementation technique and its potential for modeling with larger model sizes are discussed, and the improved results for an Encore Multimax multiprocessor are presented. © 1990 ACM.

关键词： High level languages

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computer-SYSTEM architecture CONCEPTS FOR FUTURE COMBAT SYSTEMS

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 43-62页

作者： ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin

This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st

关键词： computer architecture

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COMPARATIVE STRUCTURAL LIFE ASSESSMENT OF PATROL BOAT BOTTOM PLATING

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 253-262页

作者： AYYUB, BM WHITE, GJ BELLWRIGHT, TF PURCELL, ES Bilal M. Ayyub:is currently an associate professor of civil engineering at the University of Maryland. He received his B.S. degree in civil engineering from the University of Kuwait in 1980. He completed both his M.S. (1981) and Ph.D. (1983) in civil engineering at the Georgia Institute of Technology. Dr. Ayyub has an extensive background in risk-based analysis. He is engaged in research work involving structural reliability marine structures and mathematical modeling using the theories of probability statistics and fuzzy sets. His research work has been sponsored by the National Transportation Safety Board National Science Foundation U.S. Coast Guard Department of Defense State of Maryland and University of Maryland. He is the author of more than 100 publications in national and international journals conference proceedings and reports. Dr. Ayyub was a recipient of the ASNE “Jimmie” Hamilton Award for 1985 the ASCE “Outstanding Research Oriented Paper” in theJournal of Water Resources Planning and Managementfor 1987 and Edmund Friedman Young Engineer Award for Professional Achievement from ASCE for 1989. Gregory J. White:is an associate professor of naval architecture at the U.S. Naval Academy. He received his B.S. degreein engineering mechanics from Vanderbilt University in 1975 an M.E. degree in naval architecture from the University of California Berkeley in 1981 and a Ph.D. in civil engineering (structures) from the University of Maryland in 1986. Dr. White served on active duty with the U.S. Navy from 1975 to 1979 as a junior officer in the engineering and operations departments of Pacific Fleet destroyers. Prior to coming to the Naval Academy he worked at Mare Island Naval Shipyard in the scientific code and in the R&D division of Exxon International company's Tanker Department. Dr. White is the author of more than two dozen technical articles and reports and is one of the U.S. representatives to the International Ship and Offshore Structures Congress (ISSC). His research interests lie in t

The estimation of an absolute life expectancy of a structure is a complex process and the results are expected to have relatively large levels of uncertainty. In this study, a comparative analysis is undertaken between two different patrol boats. This is an approach which results in a higher confidence level because certain factors common to both boats can be eliminated by assuming them to be at constant normal levels. The study is limited to the critical forward bottom plating and takes into account the differences in material, plate dimensions, operational profile, structure and loading of the two vessels. Two failure modes, plastic plate deformation and fatigue, are considered, and a novel approach to plate wastage is included. Many factors affect the structural life of a vessel. They include structural type, operational profile, structural details, loads, inspection and maintenance, design methods, safety factors, corrosion, and environmental factors. There are three types of uncertainty associated with these factors; namely, physical randomness, statistical uncertainties, and model uncertainties. The method described is designed to address these uncertainties. The objective of the paper is to present the reliability-based structural life assessment method, and then to use it to evaluate and compare the structural performance of the forward bottom plating of the two patrol boats. The results of the evaluation are presented in the form of graphs and tables in order to facilitate the comparative evaluation. The method is performed within a computer-based format which allows parametric sensitivity analysis of several variables including the size of the plating panel, thickness, operational profile and loading. The sensitivity of the structural life expectancy of the forward bottom plating to variations in these parameters is evaluated.

关键词： Naval Vessels

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Data buffering: run-time versus compile-time support

Data buffering: run-time versus compile-time support

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Third International Conference on Architectural Support for Programming Languages and Operating Systems Architectural Support for Programming Languages and Operating Systems

作者： Mulder, Hans Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology PO Box 5031 2600 AG Delft The Netherlands

ISBN: (纸本)0897913000

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion

关键词： computer operating systems

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A flexible VLSI core for an adaptable architecture 22

A flexible VLSI core for an adaptable architecture

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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Stravers, Paul Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The SCalable architecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures;tools for synthesizing architectures from application or application-area;VLSI cell libraries and tools for quick generation of application-specific processors;a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates on the micro-architecture framework of SCARCE and outlines the process of generating VLSI processors. © 1990 ACM.

关键词： Cost effectiveness

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Cost-effective design of application specific VLIW processors using the SCARCE framework 22

Cost-effective design of application specific VLIW processor...

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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Portier, Robert J. Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs;especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism. The SCARCE (SCalable architecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space. This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework. © 1990 ACM.

关键词： Very long instruction word architecture

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A Necessary and Sufficient Condition for the Total Unimodularity of a Matrix in Terms of Graph Theory

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Optimization 1989年第6期20卷 901-914页

作者： Hempel, L. Herrmann, U. Hölzer, W. Wetzel, R. Weimar College of Architecture and Civil Engineering Department of Computer Science and Mathematics Germany Leipzig Institute of Technology Department of Mathematics and Computer Science Germany

We present a necessary and sufficient condition for an arbitrary matrix A to be totally unimodular. The matrix A is interpreted as the adjacency matrix of a bipartite graph G(A). The total unimodularity of A corresponds to non-existence of a cycle in G(A) which has an odd columnvaluation and which is equal to the induced subgraph. Some applications of the results are also discussed. © 1989, Taylor & Francis Group, LLC. All rights reserved.

关键词： Bipartite graphs Multicommodity flow Perfect matching Total unimodularity

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An architecture framework for application-specific and scalable architectures 89

An architecture framework for application-specific and scala...

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Proceedings of the 16th annual international symposium on computer architecture

作者： J. M. Mulder R. J. Portier A. Srivastava R. in't Velt Section Digital Systelns and Computer Architecture Department of Electrical Engineering Delft University of Technology POBox 5031260O AG Delft The Netherlands

ISBN: (纸本)9780897913195

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each *** SCalable architecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.

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Preface

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 1989年 366 LNCS卷 V-IV页

作者： Odijk, Eddy A. M. Rein, Martin Syre, Jean-Claude Philips Research Laboratories Computer Architecture P.O. Box 80.000 Eindhoven5600 JA Netherlands Department of Computer Science Eindhoven University of Technology P O. Box 513 Eindhoven5600 MB Netherlands ECRC European Computer Industry Research Centre Computer Architecture Arabellastr. 17 München 81D-8000 Germany

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