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International Symposium on Telecommunications

作者： G. Amvame-Nze Flavio E. de Deus Roque Lambert C. Jacy Barenco Abbas L. J. Garcia Villalba Electrical Engineering Department University of Brasilia Brasilia Brazil Department of. Computer Systems and Programming Complutense University of Madrid Spain

ISBN: (纸本)9781424436446

This work presents the performance of WLAN and MANET networks using the auto-configuration of Mobile IP Agents Protocol (DRMIPA). This scheme would allow groups of MIP nodes in WLANs or MANETs to enjoy IP mobility at any foreign or local network that doesn't implement MIP. To maintain a failure free MIP network, a passive agent is elected from an active agent if this active agent leaves or ceases its participation from current network. The DRMIPA protocol is implemented in WLAN and MANET. A performance analysis is done using a real world testbed scenario.

关键词： Wireless LAN Mobile ad hoc networks Home automation IP networks Protocols Ad hoc networks Fault tolerance Mobile agents Nominations and elections Proposals

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Model checking

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作者： Berg, Therese Raffelt, Harald Computer Science Department Uppsala University Sweden Department of Programming Systems and Compiler Construction University of Dortmund Germany

ISBN: (纸本)3540262784

In this chapter an introduction to model checking and model learning was given. Furthermore, it was shown how to combine both techniques to an approach in which properties of a SUT are verified directly. First of all we have presented Kripke transition systems which build a simple basis for temporal logics used in model checking. The essential difference between linear time logics and branching time logics was made plain on the basis of an example. Subsequently we presented linear time logic (LTL) and computational tree logic (CTL) which are widely used for model checking purposes. Since the combination of model checking and model learning for testing purposes is only meaningful with linear time logics we presented a basic model checking algorithm for linear time logic. In the second part of the chapter we first gave an introduction to the general ideas of model learning algorithms. Continuing in the same subject, we presented a number of learning algorithms;the observation pack algorithm, Angluin's algorithm, the reduced observation table algorithm and, the discrimination tree algorithm. Subsequently we discussed the algorithms' query complexity and presented some domain specific optimizations to reduce the number of queries. We rounded the model learning part off with some experimental results. The final part in this chapter presented the adaptive model checking algorithm, which combines model checking and model learning into one approach. The approach try to make use of information in an existing model of the SUT in order to save effort in the learning procedure. If no model exist or the existing model is irrelevant compared to the current SUT, the approach is still applicable. Although model checking and model learning are both established research areas, a lot of work remains to be done when considering testing. The combination of model checking and testing techniques should be clarified. Models to be used for testing might ask for different characteristics of

关键词： Model checking

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Strict bidirectional type checking

Strict bidirectional type checking

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TLDI'05: 2005 ACM SIGPLAN International Workshop on Types in Languages Design and Implementation

作者： Chlipala, Adam Petersen, Leaf Harper, Robert Computer Science Division University of California Berkeley United States Programming Systems Laboratory Intel Corporation United States Computer Science Department Carnegie Mellon University United States

ISBN: (纸本)1581139993

Completely annotated lambda terms (such as are arrived at via the straightforward encodings of various types from System F) contain much redundant type information. Consequently, the completely annotated forms are almost never used in practice, since partially annotated forms can be defined which still allow syntax directed type checking. An additional optimization that is used in some proof and type systems is to take advantage of the context of occurrence of terms to further elide type information using bidirectional type checking rules. While this technique is generally effective, we show that there exist bidirectional terms which exhibit asymptotic increases in the size of their type decorations when sequentialized into a named-form calculus (a common first step in compilation). In this paper, we introduce a refinement of the bidirectional type system based on strict logic which allows additional type decorations to be eliminated, and show that it is well-behaved under sequentialization. Copyright 2005 ACM.

关键词： Information theory

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The use of a Reasoning process to solve the almost SLAM Challenge at the Robocup legged league

The use of a Reasoning process to solve the almost SLAM Chal...

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8th Catalan Conference on Artificial Intelligence, CCIA 2005

作者： Monferrer, M. Teresa Escrig Broch, Juan Carlos Peris Jaume I University Engineering and Computer Science Department Campus Riu Sec CastellónE-12071 Spain Jaume I University Programming Languages and Computer Systems Department Campus Riu Sec CastellónE-12071 Spain

ISBN: (纸本)1586035606

The problem that a robot navigates autonomously through its environment, builds its own map and localizes itself in the map (known a the SLAM problem), is still an open problem. Most of the approaches to solve the SLAM problem divide the space into regions and compute the probability that the robot is in each region. We propose in this paper a different solution based on the use of a reasoning process to build the map, which will provide the following advantages: (1) we will store in the map hybrid (qualitative + quantitative) information from landmarks. Qualitative representation will allow us the management of the uncertainty information provided by the robot sensors;and (2) we will store in the map relative information of the landmarks which appear in the environment, therefore the map will be independent of the point of view of the robot. Moreover, we are going to use a reasoning process which will allow us to solve three very important problems in robotics: (a) where the robot is;(b) which is the orientation of the map where the robot is;and (c) towards where the robot should go according to the map to follow a plan. © 2005 The authors. All rights reserved.

关键词： Robots

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A dynamic compilation framework for controlling microprocessor energy and performance

A dynamic compilation framework for controlling microprocess...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Qiang Wu V.J. Reddi Youfeng Wu Jin Lee D. Connors D. Brooks M. Martonosi D.W. Clark Depts. of Computer Science Electrical Engineering Princeton University USA Department of Electrical and Computer Engineering University of Colorado Boulder USA Programming Systems Laboratory Intel Corporation USA Division of Engineering and Applied Science Harvard University USA

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control

关键词： Dynamic compiler Microprocessors Performance loss Voltage control Hardware Energy measurement Dynamic voltage scaling Frequency Energy management Microarchitecture

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Optimised asynchronous self-timing for superconducting RSFQ logic circuits

Optimised asynchronous self-timing for superconducting RSFQ ...

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AFRICON Conference

作者： H.R. Gerber C.J. Fourie W.J. Perold Applied computer programming and computer systems Electronics and quantum electronics Department of Electronic and Electrical Engineering University of Stellenbosch

Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested

关键词： Superconducting logic circuits Logic circuits Clocks Timing Logic testing Digital circuits Logic gates Design methodology Circuit testing Adders

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Improving grammar-based evolutionary algorithms via attributed derivation trees

Improving grammar-based evolutionary algorithms via attribut...

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7th European Conference on Genetic programming, EuroGP 2004

作者： Zvada, Szilvia Ványi, Róbert Department of Programming Systems Friedrich-Alexander University Martensstraße 3 ErlangenD-91058 Germany Department of Theoretical Computer Science Friedrich-Alexander University Martensstraße 3 ErlangenD-91058 Germany

ISBN: (纸本)3540213465

Using Genetic programming difficult optimization problems can be solved, even if the candidate solutions are complex objects. In such cases, it is a costly procedure to correct or replace the invalid individuals that may appear during the evolutionary process. Instead of such post-processing, context-free grammars can be used to describe the syntax of valid solutions, and the algorithm can be modified to work on derivation trees, such that it does not generate invalid individuals. Although tree operators have the advantage of good parameterizability, it is not trivial to construct them correctly and efficiently. In this paper an already existing method for derivation tree evolution and its extension towards attributed derivation trees are discussed. As the result of this extension the operators are not only faster but they are easy to parameterize, moreover the algorithm is better guided, thus it can converge faster. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Genetic programming

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Authentication and autoconfiguration for MANET nodes

Authentication and autoconfiguration for MANET nodes

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International Conference on Embedded and Ubiquitous Computing, EUC 2004

作者： Buiati, Fabio Puttini, Ricardo De Sousa, Rafael Barenco Abbas, C.J. García Villalba, L.J. University of Brasília Department of Electrical Engineering Brasília70910-900 Brazil Department of Computer Systems and Programming Complutense University of Madrid–UCM Juan del Rosal 8 DespachoMadrid431 28040 Spain

ISBN: (纸本)354022906X

In this paper we propose a secure autoconfiguration model for Manet. Our design is based in a distributed and self-organization certification service, which provides node identification and authentication for the autoconfiguration protocol. We have defined some modifications in the Dynamic Configuration and Distribution Protocol (DCDP) in order to extend the protocol functionalities to include security-aware node identification and authentication services. The overall security is also enforced with intrusion detection techniques. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Intrusion detection

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Preface

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2004年 2981卷 V-VI页

作者： Müller-Schloer, Christian Ungerer, Theo Bauer, Bernhard University of Hannover Institute of Systems Engineering System and Computer Architecture - SRA Appelstr. 4 Hannover Germany University of Augsburg Institute of Informatics Augsburg Germany University of Augsburg Department of Software Engineering and Programming Languages Augsburg Germany

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Good error correcting output codes for adaptive multiclass learning

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4th International Workshop on Multiple Classifier systems, MCS 2003

作者： Tapia, Elizabeth González, José Carlos García-Villalba, Javier Department of Electrical Engineering National Univ. of Rosario Argentina Department of Telematics Engineering Technical Univ. of Madrid Spain Department of Computer Systems and Programming Complutense Univ. of Madrid Spain

ISBN: (纸本)3540403698

In recent work, we introduced a generalization of ECOC learning under the theory of recursive error correcting codes. We named it RECOC (Recursive ECOC) learning. If long output codewords are allowed, as in the case of problems involving a large number of classes, standard recursive codes such as LDPC or Turbo can be used. However, if the number of classes is moderated, neither good LDPC nor Turbo codes might exist due to the small block lengths involved. In this paper, RECOC learning based on the recently introduced ensemble of Product Accumulated codes is analyzed. Due to their native data storage oriented design, smaller block lengths are allowed. In addition, because of their simplicity, all key concepts regarding RECOC learning can be easily explained. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Digital storage

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