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arXiv 2024年

作者： Hong, Q.Y. Antolin, P. Elber, G. Kim, M.-S. Hanyang University ERICA Department of Computer Science and Engineering Ansan Korea Republic of Ecole Polytechnique Federale de Lausanne Institute of Mathematics Lausanne Switzerland Techion - Israel Institute of Technology Department of Computer Science Haifa Israel Seoul National University Department of Computer Science and Engieering Seoul Korea Republic of

The synthesis of porous, lattice, or microstructure geometries has captured the attention of many researchers in recent years. Implicit forms, such as triply periodic minimal surfaces (TPMS) has captured a significant attention, recently, as tiles in lattices, partially because implicit forms have the potential for synthesizing with ease more complex topologies of tiles, compared to parametric forms. In this work, we show how variable offsets of implicit forms could be used in lattice design as well as lattice analysis, while graded wall and edge thicknesses could be fully controlled in the lattice and even vary within a single tile. As a result, (geometrically) heterogeneous lattices could be created and adapted to follow analysis results while maintaining continuity between adjacent tiles. We demonstrate this ability on several 3D models, including TPMS. Copyright © 2024, The Authors. All rights reserved.

关键词： Microstructure

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Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs

Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural ...

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Design Automation Conference

作者： Halima Bouzidi Mohanad Odema Hamza Ouarnoughi Smail Niar Mohammad Abdullah Al Faruque LAMIH/UMR CNRS Université Polytechnique Hauts-de-France Valenciennes France Department of Electrical Engineering and Computer Science University of California Irvine USA

Heterogeneous MPSoCs comprise diverse processing units of varying compute capabilities. To date, the mapping strategies of neural networks (NNs) onto such systems are yet to exploit the full potential of processing parallelism, made possible through both the intrinsic NNs’ structure and underlying hardware composition. In this paper, we propose a novel framework to effectively map NNs onto heterogeneous MPSoCs in a manner that enables them to leverage the underlying processing concurrency. Specifically, our approach identifies an optimal partitioning scheme of the NN along its ‘width’ dimension, which facilitates deployment of concurrent NN blocks onto different hardware computing units. Additionally, our approach contributes a novel scheme to deploy partitioned NNs onto the MPSoC as dynamic multi-exit networks for additional performance gains. Our experiments on a standard MPSoC platform have yielded dynamic mapping configurations that are 2.1x more energy-efficient than the GPU-only mapping while incurring 1.7x less latency than DLA-only mapping.

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Securing Overlay Cognitive Radio Networks Over Cascaded Channels with Energy Harvesting

Securing Overlay Cognitive Radio Networks Over Cascaded Chan...

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IEEE Globecom Workshops

作者： Deemah H. Tashman Soumaya Cherkaoui Walaa Hamouda Sidi Mohammed Senouci Department of Computer and Software Engineering Polytechnique Montreal Montreal Canada Department of Electrical and Computer Engineering Concordia-University Montreal Canada DRIVE Laboratory EA1859 Univ. Bourgogne Franche Comté Nevers France

This paper investigates the physical-layer security (PLS) for an overlay cognitive radio network (CRN). Due to the unreliability of direct communication between the primary users (PUs), secondary users (SUs) are enlisted to facilitate communication between two PUs. As several SUs are available, a particular one is chosen to transmit the PUs' messages in addition to its own. This SU uses the time switching protocol to harvest power from the PU's signal. Additionally, an eavesdropper is available to capture the messages conveyed by the PUs. Given this, the SU receiver collects energy from the relayed messages through the power splitting protocol and utilizes this energy to transmit jamming signals in order to degrade the wiretap channel and improve the privacy of the PUs' communication. The signals' transmission is modeled more realistically under the assumption of cascaded Rayleigh channels. The performance of PLS is evaluated using the probability of a non-zero secrecy capacity and the intercept probability. Moreover, the SUs' Ergodic rate is studied to analyze the impact of this assistance on their transmission reliability.

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Detection of hot electrons originating from an upper valley at ∼1.7eV above the Γ valley in wurtzite GaN using electron emission spectroscopy

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Physical Review B 2023年第3期107卷 035303-035303页

作者： Wan Ying Ho Abdullah I. Alhassan Cheyenne Lynsky Yi Chao Chow Daniel J. Myers Steven P. DenBaars Shuji Nakamura Jacques Peretti Claude Weisbuch James S. Speck Materials Department University of California Santa Barbara Santa Barbara California 93106-5050 USA Department of Electrical and Computer Engineering University of California Santa Barbara Santa Barbara California 93106-5050 USA Laboratoire de Physique de la Matière Condensée CNRS Ecole Polytechnique IP Paris 91128 Palaiseau France

Using electron emission spectroscopy, measurement and analysis were conducted on the energy distribution of vacuum emitted electrons from electrically driven InGaN/GaN green (peak wavelengths λ≈515nm) light-emitting diodes (LEDs) with and without a prewell superlattice (SL). We report on the detection of a high-energy upper valley at ∼1.7eV above the Γ valley from samples with no prewell SL. We propose that these upper valley electrons originate predominantly from trap-assisted Auger recombination (TAAR) in green LEDs, as the intensity of these peaks is found to have quadratic dependence on the carrier density n [see Espenlaub et al., J. Appl. Phys. 126, 184502 (2019)]. The high-energy upper valley peak was not observed in the sample with a prewell SL which is attributed to gettering by the prewell SL of still unidentified impurities that act as TAAR centers.

关键词： Carrier generation & recombination Electroluminescence Electron emission Electronic structure Optoelectronics

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Blockchain, AI and Smart Grids: The Three Musketeers to a Decentralized EV Charging Infrastructure

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IEEE Internet of Things Magazine 2020年第2期3卷 24-29页

作者： Elhusseini, Hossam Assi, Chadi Moussa, Bassam Attallah, Ribal Ghrayeb, Ali Department of Electrical and Computer Engineering Texas AandM University Qatar Concordia University Canada Polytechnique Montreal Canada

The proliferation of Internet of Things (IoT) has brought an array of different services, from smart health-care, to smart transportation, all the way to smart cities. For a truly connected environment, different sectors need to collaborate. One use case of such overlap is between smart grids and Intelligent Transportation System (ITS) giving rise to Electric Vehicles and their charging infrastructure. Being such a lucrative opportunity for investors and the research community, many efforts have been made toward providing the end-user with an extraordinary Quality of Service (QoS). However, given the current protocols and deployment of the Electric Vehicle (EV) charging infrastructure, some key challenges still need to be addressed. In particular, we identify two main EV challenges: (1) vulnerable charging stations and EVs, and (2) non-optimal charging schedules. With these issues in mind, we evaluate the integration of Blockchain and AI with the EV charging infrastructure. Specifically, we discuss the current AI and Blockchain charging solutions available in the market. In addition, we propose a couple of use cases where both technologies complement each other for a secure, efficient and decentralized charging ecosystem. This article serves as starting point for stakeholders and policymakers to help identify potential directions and implementations of better charging systems for EVs. © 2018 IEEE.

关键词： Blockchain

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HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling

HADAS: Hardware-Aware Dynamic Neural Architecture Search for...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Halima Bouzidi Mohanad Odema Hamza Ouarnoughi Mohammad Abdullah Al Faruque Smail Niar LAMIH/UMR CNRS Université Polytechnique Hauts-de-France Valenciennes France Department of Electrical Engineering and Computer Science University of California Irvine USA

Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In many cases, the implementation of DyNNs can be sub-optimal due to its underlying backbone architecture being developed at the design stage independent of both: (i) potential support for dynamic computing, e.g. early exiting, and (ii) resource efficiency features of the underlying hardware, e.g., dynamic voltage and frequency scaling (DVFS). Addressing this, we present HADAS, a novel Hardware-Aware Dynamic Neural Architecture Search framework that realizes DyNN architectures whose backbone, early exiting features, and DVFS settings have been jointly optimized to maximize performance and resource efficiency. Our experiments using the CIFAR-100 dataset and a diverse set of edge computing platforms have shown that HADAS can elevate dynamic models' energy efficiency by up to 57% for the same level of accuracy scores. Our code is available at https://***/HalimaBouzidi/HADAS

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Real-time 3D Shape Sensing with a Random Fiber Bragg Grating Triplet

Real-time 3D Shape Sensing with a Random Fiber Bragg Grating...

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Optical Sensors, Sensors 2022

作者： Francoeur, Jacynthe Roberge, Anthony Lorre, Pierre Monet, Frédéric Wright, Cory Kadoury, Samuel Kashyap, Raman Department of Electrical Engineering École Polytechnique Montréal 2500 Chem. de Polytechnique MontréalQCH3T 1J4 Canada Department of Physics Engineering École Polytechnique Montréal 2500 Chem. de Polytechnique MontréalQCH3T 1J4 Canada Research and Development Boston Scientific 4100 Hamline Ave N Arden HillsMN55112 United States Department of Computer and Software Engineering École Polytechnique Montréal 2500 Chem. de Polytechnique MontrealQCH3T 1J4 Canada

Using an optical frequency domain reflectometry (OFDR) technique, real-time 3D shape sensing of simple and complex bends with an extruded optical fiber triplet with enhanced backscatter power is demonstrated. © 2... 详细信息

ISBN: (纸本)9781557528209

关键词： Fiber Bragg gratings

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Design of a Reconfigurable Activation Function for All-Optical Neural Networks

Design of a Reconfigurable Activation Function for All-Optic...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Oceane Destras Sébastien Le Beux Felipe Gohring de Magalhaes Gabriela Nicolescu Département de génie informatique et génie logiciel Polytechnique Montreal Montreal QC Canada Department of Electrical and Computer Engineering Concordia University Montreal QC Canada

ISBN: (数字)9798350361759

ISBN: (纸本)9798350361766

Photonic integrated circuits present a promising avenue for the integration of Deep Neural Networks (DNNs), offering solutions to the speed and power consumption constraints inherent to their electronic counterparts. Notably, research showcasing the ability of photonic integrated circuits to realize matrix multiplications - a crucial operation in DNNs - at the speed of light has drawn much attention to the field of optical neural networks (ONNs). One of the challenges of designing fully optical DNNs is the photonic integration of the activation function, a nonlinear function. Optical nonlinear responses often deviate in shape from traditional DNN activation functions. A pivotal requirement for standardizing ONN architectures without sacrificing flexibility is the development of a fully tunable optical activation function. Presently, reconfigurable optical activation functions exhibit limitations in reproducing diverse functions, constraining the potential of photonic DNNs. In this article, we propose an architecture leveraging Mach-Zehnder interferometers and saturable absorbers to execute a range of activation functions, including ReLU, sigmoid, and tanh.

关键词： Integrated optics Training Optical interferometry Photonic integrated circuits Optical computing Artificial neural networks Optical fiber networks

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Hardware Acceleration of Capsule Networks for Real-Time Applications

Hardware Acceleration of Capsule Networks for Real-Time Appl...

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Euromicro Symposium on Digital System Design

作者： Maryam Hemmati Earlene Starling Babette Julia Shan Morteza Biglari-Abhari Smail Niar Department of Electrical Computer and Software Engineering The University of Auckland Auckland New Zealand CNRS LAMIH and INSA Hauts-de-France Univ. Polytechnique Hauts-de-France Valenciennes France

ISBN: (数字)9798350380385

ISBN: (纸本)9798350380392

Capsule networks (CapsNet) are a category of deep learning neural networks (DNN) that address one of the main issues and deficiencies of convolutional neural networks (CNN); loss of spatial information in pooling layers. However, the main concern with CapsNets is their compute-intensive nature, which is mainly related to the vector-based calculations during dynamic routing and acts as a barrier for their deployment in real-time applications. To address the specific computing requirements of dynamic routing in capsule layers of CapsN ets, we develop a hardware accelerator for dynamic routing using Vitis HLS. In this paper, we present a hardware acceleration solution for capsule networks by integrating AMD Xilinx deep processing unit (DPU) and a custom accelerator for the capsule layer. Our results show significant improvement in throughput compared with the baseline implementation when CapsNet is implemented on Zynq UltraScale+ MPSoC ZCU102 usinz Vitis AI DPUs.

关键词： Program processors Digital systems Neural networks C++ languages Routing Throughput Real-time systems Convolutional neural networks Artificial intelligence Hardware acceleration

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Learning to remove cuts in integer linear programming 24

Learning to remove cuts in integer linear programming

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Proceedings of the 41st International Conference on Machine Learning

作者： Pol Puigdemont Stratis Skoulakis Grigorios G Chrysos Volkan Cevher LIONS École Polytechnique Fédérale de Lausanne Switzerland and Universitat Politècnica de Catalunya (UPC) Spain LIONS École Polytechnique Fédérale de Lausanne Switzerland Department of Electrical and Computer Engineering University of Wisconsin-Madison

Cutting plane methods are a fundamental approach for solving integer linear programs (ILPs). In each iteration of such methods, additional linear constraints (cuts) are introduced to the constraint set with the aim of excluding the previous fractional optimal solution while not affecting the optimal integer solution. In this work, we explore a novel approach within cutting plane methods: instead of only adding new cuts, we also consider the removal of previous cuts introduced at any of the preceding iterations of the method under a learnable parametric criteria. We demonstrate that in fundamental combinatorial optimization settings such cut removal policies can lead to significant improvements over both human-based and machine learning-guided cut addition policies even when implemented with simple models.

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