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检索条件"机构=Department for Design Problems in Microelectronics"

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Adaptive Arrays Based on Real-Valued Arithmetic Linearly-Constrained IQRD RLS Adaptive Filtering Algorithms 3

Adaptive Arrays Based on Real-Valued Arithmetic Linearly-Con...

引用

3rd IEEE Ukraine Conference on Electrical and Computer Engineering, UKRCON 2021

作者： Djigan, Victor Institute for Design Problems in Microelectronics of RAS Department of Integrated Circuits Design Methodology Moscow Russia

ISBN: (纸本)9781665400947

This paper presents computational procedures for implementation of multi-beam adaptive antenna arrays with digital beamforming. The weights of the arrays are calculated using the Linearly Constrained Inverse QR Decomposition Recursive Least Squares adaptive filtering algorithms. Two versions of the algorithms are presented: With and without square roots arithmetic operations. The algorithms are fitted to the antenna arrays with odd symmetry. This symmetry allows to develop the adaptive filtering algorithms with most of the computations in real-valued arithmetic. This saves the number of the arithmetic operations required per algorithm iteration. Besides, this implementation decreases the transient response duration and improves the steady-state interference cancellation for about 3 dB in terms of the depths of the radiation pattern gaps towards the interference sources. The efficiency of the proposed solution is demonstrated via simulation of interference cancellation using a rectangular flat adaptive antenna array. © 2021 IEEE.

关键词： Adaptive filters

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Application of Affine Projection Algorithm in Adaptive Arrays 3

Application of Affine Projection Algorithm in Adaptive Array...

引用

3rd IEEE Ukraine Conference on Electrical and Computer Engineering, UKRCON 2021

作者： Djigan, Victor Institute for Design Problems in Microelectronics of RAS Department of Integrated Circuits Design Methodology Moscow Russia

ISBN: (纸本)9781665400947

This paper considers the Linearly Constrained (LC) Affine Projection (AP) adaptive filtering algorithm and its application in adaptive antenna arrays. The proposed version of the algorithm has a reduced number of computations comparing with that of the original algorithm. It is shown that the normalization matrix and its inverse, which appear in the AP algorithm, can be computed with a reduced number of arithmetic operations due to the specific structure of the matrices. The details of the algorithm development and the full computational procedure of the algorithm are presented. The algorithm efficiency is demonstrated via the simulation of the interference mitigation by means of the proposed AP algorithm in a rectangular adaptive antenna array. It is shown that the usage of the algorithm projection order, which equals just 2, allows to increase the depths of the steady-state radiation pattern gaps towards the interference sources about 7 dB in comparison with that of the LC Normalized Least Mean Square algorithm in the same operation conditions. The further increase of the projection order improves the AA performance too, but the improvement is not so significant. So, the projection order can be restricted by the values of 2... 4, that leads to the low complexity of the AP algorithm. © 2021 IEEE.

关键词： Adaptive filters

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Some Tricks of Calculations in MIL RLS Algorithm 23

Some Tricks of Calculations in MIL RLS Algorithm

引用

23rd International Conference on Digital Signal Processing and its Applications, DSPA 2021

作者： Djigan, Victor Institute for Design Problems in Microelectronics of RAS Department of Integrated Circuits Design Methodology Moscow Russia

ISBN: (纸本)9781728195513

This paper presents two optimized computational procedures of the Recursive Least Squares (RLS) adaptive filtering algorithm based on the Matrix Inversion Lemma (MIL). The traditional MIL RLS algorithm might be unstable due to the accumulation of the errors of the computations. These errors are the reasons of the loss of the Hermitian structure of the adaptive filter input signal correlation matrix. As a result, the matrix becomes noninvertible and this leads to the wrong calculation of the weighs and the unstable behavior of the adaptive filter. In this paper it is suggested to compute the main diagonal and only the upper or the lower diagonal part of the correlation matrix. The rest of the computations, required at each iteration, are executed assuming the Hermitian structure of the whole matrix. In this case, no loss of the matrix symmetry appears. This ensures the optimized MIL RLS algorithm stability that is demonstrated via the simulation of an adaptive antenna array. The optimization also decreases the MIL RLS algorithm complexity. This is demonstrated via the estimates of the number of the arithmetical operations per iteration of the traditional MIL RLS algorithm, its optimized versions and RLS algorithms based on the QR decomposition and Householder transform. © 2021 IEEE.

关键词： Adaptive filters

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Circular Adaptive Antenna Array

Circular Adaptive Antenna Array

引用

2021 IEEE East-West design and Test Symposium, EWDTS 2021

作者： Djigan, Victor Institute for Design Problems in Microelectronics of RAS Design Methodology Department of Integrated Circuits Moscow Russia

ISBN: (纸本)9781665445030

The widely used linear or flat adaptive antenna arrays have a drawback that is the non-fixed beamwidth. The width increases, as the beam steering direction moves from the aperture normal to the aperture plane. If it is required the beam steering over a wide range of angles, then it restricts such an array application. This drawback is absent in the circular antenna arrays. Such arrays are attractive for the usage in the communication applications, because they provide 360° beam scanning with the fixed beamwidth. Additionally, the usage of the adaptive signal processing allows these arrays to combat the interferences and it is very important for the communication systems, which share the same frequency band. This paper considers the adaptive antenna arrays with circular antenna placement. The performance of the circular adaptive array, which uses the Recursive Least Squares algorithm, is demonstrated. The simulation confirms the circular array ability to provide the beam steering over a wide range of angles with the fixed beamwidth and to suppress the interferences simultaneously. © 2021 IEEE.

关键词： Smart antennas

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Development of Visualization Algorithms for Digital Integrated Circuits at the Gate Level

Development of Visualization Algorithms for Digital Integrat...

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Electrical Engineering, Automation & Control Systems, Theory and Practical Applications (EEACS), Seminar on

作者： Gorislav I. Goglev Ivan V. Tiunov CAD Department Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

Graphical user interface is an inherent part of any modern computer aided design system, especially in micro- and nanoelectronics area. Carefully developed interface can notably simplify and boost up the integrated circuits design process. The proposed paper studies the problem of developing the placement and routing algorithms that are essential for solving the problem of digital integrated circuits visualization. These algorithms are the basis of a graphical design tool for digital circuits at the gate level. The suggested algorithms are built upon such known methods as ranking-based placement and Mikami-Tabuchi routing algorithm. In the paper, a graph model for a digital circuit representation and software implementation aspects are also proposed. The visualization results of some circuits from ISCAS'89 testbench are represented.

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Applying Machine Learning Methods to Signal Integrity Analysis

Applying Machine Learning Methods to Signal Integrity Analys...

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2024 Ivannikov Open Conference, ISPRAS 2024

作者： Zhigulin, Alexey Rogozhinskiy, Mikhail Solovyev, Roman Telpukhov, Dmitriy Levchenko, Nikolay Stempkovskiy, Alexander Pereverzev, Leonid AlphaCHIP LLC Dept. of Automation of Design of Integrated Circuits Moscow Russia AlphaCHIP LLC Dept. of Design of Integrated Circuits Moscow Russia AlphaCHIP LLC Innovation Activities Moscow Russia AlphaCHIP LLC Deputy General Director for Research Moscow Russia NRC 'Kurchatov Institute' Department for Design Problems in Microelectronics Moscow Russia AlphaCHIP LLC Moscow Russia

ISBN: (纸本)9798331526023

Voltage spikes caused by signal switching in adjacent circuits can lead to false switching and failures in integrated circuits. To identify such risks, signal integrity (SI) analysis is performed by extracting parasitic RC networks, followed by SPICE simulation or application of analytical methods. However, this process is time-consuming. This research proposes using machine learning methods to rapidly and accurately predict the results of SI analysis without the need for computationally expensive modeling. It accelerates SI analysis a lot with low accuracy losses. Also, this paper introduces new reduction model for victim-aggressor pair that is more accurate than previously used. © 2024 IEEE.

关键词： Adversarial machine learning

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Static Timing Analysis Method for Reconfigurable SoC with Various Types of Routing Resources

Static Timing Analysis Method for Reconfigurable SoC with Va...

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Electrical Engineering, Automation & Control Systems, Theory and Practical Applications (EEACS), Seminar on

作者： Vasilii M. Khvatov Computer Aided Design Department Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

Reconfigurable systems on a chip (RSoC) routing tree architecture consists of both digital elements and MOS switches. To evaluate the performance of routed integrated circuits (ICs), a netlist and a library of characterized elements is required. However, the MOS switch is an analog element and models for describing the time parameters of digital cells, including the non-linear delay model, cannot be applied to it. To solve this problem, this paper proposes a method for estimating the ICs performance based on the use of the connections equivalent electrical capacity and proposed formulas for calculating time parameters. The formulas were obtained as a result of researching the dependence of circuit timing characteristics on three parameters: the number of pass switches in the net, the load capacitance and the parameters of transistors at the output stage of the routing element. The approach allows to calculate the output signal parameters for various types of RSoC routing elements, including pass transistors, without critical losing of accuracy.

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Backpass Trees for Modifying PathFinder-based Routing Algorithm for FPGA

Backpass Trees for Modifying PathFinder-based Routing Algori...

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IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, SIBIRCON

作者： Alexander Y. Chistiakov Mariya A. Zapletina Sergey V. Gavrilov CAD Department Institute for Design Problems in Microelectronics of RAS Zelenograd Russia Administration Department Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (纸本)9781665464819

In the field-programmable gate array and programmable system-on-a-chip design flow routing is a highly time-consuming stage that provides the last opportunity to make any design optimizations. Therefore, reducing its runtime with no significant losses in a quality of result occurs to be an extremely important problem to solve. This paper proposes a modification of a PathFinder-based algorithm to implement a directed search technique which contributes FPGA routing acceleration. The main idea is to direct the searching process by routing graph connectivity consideration in a form of backpass trees. The modification is relevant for the situation when there are no geometric coordinates known for FPGA/PSoC routing resources. The modified algorithm was tested on IWLS’2005 and some commercial benchmark sets. The obtained experimental results demonstrate an average runtime reduction by 10% while the average critical path delay and wirelength slightly increase (1.8% and 0.3% respectively) caused by usage of the introduced backpass trees structures.

关键词： Runtime design automation Forestry Benchmark testing Routing Delays System-on-chip

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Simple Algorithms for Antenna Array Calibration and Their Accuracy 3

Simple Algorithms for Antenna Array Calibration and Their Ac...

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3rd IEEE Ukraine Conference on Electrical and Computer Engineering, UKRCON 2021

作者： Kurganov, Vladislav Djigan, Victor Moscow Russia Institute for Design Problems in Microelectronics of RAS Department of Integrated Circuits Design Methodology Moscow Russia

ISBN: (纸本)9781665400947

This paper presents two simple algorithms, developed for the calibration of antenna arrays (AA), which do not require phase measurements. The algorithms estimate the unknown AA channel phases by means of the solution of a system of real-valued linear equations. The data, which are used in these equations, are the AA output power measurements under the perturbation of the current phase shifter state on 0°, 90° and 270° or on 0°, 90° and 180° in each calibrated channel. The paper presents the mathematical details of the proposed algorithms. The simulation results demonstrate the accuracy of the algorithms in terms of the mean square errors of the estimated channel phases and in terms of the Euclidian distance between the radiation pattern of the ideal AA and the calibrated AA, i.e. the AA whose channel phases are estimated and compensated. Additionally, this accuracy is compared to that of the simplified versions of the Rotating-Element Electric-Field Vector (REV) algorithm. The new algorithms can be used not only for the AA calibration in the anechoic chamber, but also in the field operation, providing the AA calibration and signal source tracking simultaneously. © 2021 IEEE.

关键词： Antenna arrays

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Hardware Implementation of Convolutional Neural Network Based on Systolic Matrix Multiplier

Hardware Implementation of Convolutional Neural Network Base...

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Intelligent Technologies and Electronic Devices in Vehicle and Road Transport Complex (TIRVED)

作者： Alexander Stempkovskiy Roman Solovyev Dmitry Telpukhov Alexander Kustov Department of Design Methodology of Integrated Circuit Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

In this paper, we consider possibility of using matrix multipliers in hardware implementation of convolutional neural networks. Literature review has been conducted, existing matrix multiplication methods and their hardware implementations has been analyzed. Systolic algorithm for matrix multiplication (SMM) based on divide-and-conquer approach is proposed. This algorithm has been implemented as parameterized generator of hardware descriptions. Its positive and negative aspects are identified. Main difficulties of preparing feature maps for matrix multiplication are analyzed. Comparative analysis of hardware implementations of MobileNet neural network has been carried out for implementations based on convolutional blocks and implementations based on systolic matrix multiplier. A combined method is proposed that has the advantages of both approaches.

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