Extensibility, flexibility, easy maintainability, and long-term robustness are core requirements for modern, highly distributed information and computation systems. Such systems in turn show a steady increase in compl...
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The automatic programming system has been considered by means of which it becomes easier to carry out traditional programming stages. There is discussed both recursive forms: parallel, interrecursion and recursion of ...
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The automatic programming system has been considered by means of which it becomes easier to carry out traditional programming stages. There is discussed both recursive forms: parallel, interrecursion and recursion of high level that exist for functional programming languages and induction methods for the purpose of their verification. The way how to present imperative languages easy and double cycles by means of recursion forms is shown, the possibility of verification has been studied for each recursion form.
A DSM protocol ensures that a thread can access data allocated on another machine using some consistency protocol. The consistency protocol can either replicate the data and unify replica changes periodically or the t...
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ISBN:
(纸本)9780889867741
A DSM protocol ensures that a thread can access data allocated on another machine using some consistency protocol. The consistency protocol can either replicate the data and unify replica changes periodically or the thread, upon remote access, can migrate to the machine that hosts the data and access the data there. There is a performance tradeoff between these extremes. Data replication suffers from a high memory overhead as every replicated object or page consumes memory on each machine. On the other hand, it is as bad to migrate threads upon each remote access since repeated accesses to the same distributed data set will cause repeated network communication whereas replication will incur this only once (at the cost of increased administration overhead to manage the replicas). We propose a hybrid protocol that uses selective replication with thread migration as its default. Even in the presence of extreme memory pressure and thread-migrations, our protocol reaches or exceeds the performance that can be achieved by means of manual replication and explicit changes of the application's code.
As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transaction memory (TM) semantics are compli...
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ISBN:
(纸本)9781595939739
As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transaction memory (TM) semantics are complicated by the fact that programs may access the same memory locations both inside and outside transactions. Strongly atomic semantics, where non-transactional accesses are treated as implicit single-operation transactions, remain difficult to provide without specialized hardware support or significant performance overhead. As an alternative, many in the community have informally proposed that a single global lock semantics [18, 10], where transaction semantics are mapped to those of regions protected by a single global lock, provide an intuitive and efficiently implementable model for programmers. In this paper, we explore the implementation and performance implications of single global lock semantics in a weakly atomic STM from the perspective of Java, and we discuss why even recent STM implementations fall short of these semantics. We describe a new weakly atomic Java STM implementation that provides single global lock semantics while permitting concurrent execution, but we show that this comes at a significant performance cost. We also propose and implement various alternative semantics that loosen single lock requirements while still providing strong guarantees. We compare our new implementations to previous ones, including a strongly atomic STM. [24] Copyright 2008 ACM.
A class of Probabilistic Abductive Logic Programs (PALPs) is introduced and an implementation is developed in CHR for solving abductive problems, providing minimal explanations with their probabilities. Both all-expla...
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The paper presents the on-going EC-funded Tempus project "MSc and PhD studies in Aerospace Critical Computing" executed by the National Aerospace University, Kharkiv, Ukraine with the support of Newcastle Un...
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ISBN:
(纸本)9781605580760
The paper presents the on-going EC-funded Tempus project "MSc and PhD studies in Aerospace Critical Computing" executed by the National Aerospace University, Kharkiv, Ukraine with the support of Newcastle University and City University of London, UK and Åbo Akademi University, Turku, Finland. The state-of-the-art, completed work as well as the next steps of the development of master and doctoral courses for the specialty in critical software engineering, computer systems and networks are described. The inputs from each of the European consortium members are presented. Copyright 2008 ACM.
With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core p...
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ISBN:
(纸本)1595936025
With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Moore's law will largely be used to increase HW thread-level parallelism through higher core counts in a CMP environment. CMPs bring new challenges into the design of the software system stack. In this tutorial, we talk about the shift to multi-core processors and the programming implications. In particular, we focus on transactional programming. Transactions have emerged as a promising alternative to lock-based synchronization that eliminates many of the problems associated with lock-based synchronization. We discuss the design of both hardware and software transactional memory and quantify the tradeoffs between the different design points. We show how to extend the Java and C languages with transactional constructs, and how to integrate transactions with compiler optimizations and the language runtime (e.g., memory manager and garbage collection).
In this paper we advocate to introduce a common modelling pattern for all the different layers of middleware based on services. This opens the possibility to flexibly choose the adequate levels for realizing specific ...
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ISBN:
(纸本)9781595939326
In this paper we advocate to introduce a common modelling pattern for all the different layers of middleware based on services. This opens the possibility to flexibly choose the adequate levels for realizing specific features, and it allows all stakeholders to get a global picture of the overall scenario, a central factor when considering the convergence in networks and applications. Moreover, it allows to apply validations methods like model-based testing and model checking homogeneously, throughout the whole modelling hierarchy, from the underlying converging platforms to the user level. Copyright 2007 ACM.
作者：
Y. WakasaY. YamamotoDept. of Applied Analysis and Complex Dynamical Systems
Graduate School of Informatics Kyoto University Kyoto Japan. Yuji Wakasa was born in Okayama
Japan in 1968. He received the B.S. and M.S. degrees in engineering from Kyoto university Japan in 1992 and 1994 respectively. From 1994 to 1998 he was a Research Associate in the Department of Information Technology Okayama University. Since April 1998 he has been a Research Associate in the Graduate School of Informatics Kyoto University. His current research interests include robust control and control system design via mathematical programming. Yutaka Yamamoto received his B.S. and M.S. degrees in engineering from Kyoto University
Kyoto Japan in 1972 and 1974 respectively and the M.S. and Ph.D. degree in mathematics from the University of Florida in 1976 and 1978 respectively. From 1978 to 1987 he was with Department of Applied Mathematics and Physics Kyoto University and from 1987 to 1997 with Department of Applied System Science. Since 1998 he is a professor at the current position. His current research interests include realization and robust control of distributed parameter systems learning control sampled-data systems and digital signal processing. Dr. Yamamoto is a receipient of the Sawaragi memorial paper award (1985) the Outstanding Paper Award of SICE (1987) Best Author Award of SICE (1990) the George Axelby Outstanding Paper Award of IEEE CSS in 1996 Takeda Paper Prize of SICE in 1997. He is a Fellow of IEEE. He was an associate editor of Automatica. He is currently an associate editor of IEEE Transactions on Automatic Control Systems and Control Letters and Mathematics of Control Signals and Systems. He is a member of the IEEE the Society of Instrument and Control Engineers (SICE) and the Institute of Systems Control and Information Engineers.
This paper presents a design method of control systems such that a designer can flexibly take account of tradeoffs between evaluated uncertainty ranges and the level of control performance. The problem is reduced to a...
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This paper presents a design method of control systems such that a designer can flexibly take account of tradeoffs between evaluated uncertainty ranges and the level of control performance. The problem is reduced to a BMI problem and approximately solved by LMIs. The convergence of the proposed approximation is proved in a modified sense. A numerical example shows the effectiveness of the proposed method in comparison with the standard robust control.
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