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2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Xu, Min Zhou, Junrui Zhou, Wei An, Hong Department of Computer Science and Technology University of Science and Technology Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9780769545646

Distributed file system (DFS) is playing important roles of supporting large distributed data-intensive applications to meet storage needs. Typically, the design of DFS, such as GFS in Google, DMS in Cisco and TFS in Alibaba, is driven by observations of specific application workloads, internal demands and technological environment. In such systems, the metadata service is a critical factor that can affect the file system performance and availability to a great degree. Five requirements have been summarized for the metadata service: location transparent file service, smart director, efficient speed, strong scalability and friendly collaborator. In this paper, we present metadata service module called CHMasters in our DFS. Consistent hashing protocol is used to relieve potential hot spots on name servers. Files'metadata and master nodes are mapped into the same hash space by consistent hash function. And then files'metadata are scattered to master nodes by clockwise "closest" principle. Chunkserver acts as a client when report its chunks info. Only a small proportion of files'metadata will be rehashed when master nodes state change. A new scalable file mapping strategy is also proposed to map file sizes from few MB to several GB efficiently. After intensive experiments, it shows CHMasters is satisfying the above five requirements. © 2011 IEEE.

关键词： Metadata

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Advances of OPC client server architectures for maintenance strategies - A research and development area not only for industries

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WSEAS Transactions on systems and Control 2008年第3期3卷 195-207页

作者： Schwarz, M.H. Boercsoek, J. University of Kassel Department of Computer-architecture and System-programming Wilhelmshoeher Allee 34121 Kassel Germany HIMA Paul Hildebrandt GmbH + Co KG Albert-Bassermann-Str. 28 68782 Brühl Germany

OPC is a matured and accepted standard in industries, but hardly used in industrial applications developed at universities, especially in Europe. Publications in this area, either using OPC-communication or developing applications have been hardly increased over the past several years. This paper reports the current state of the standard, but also describes current problems and how they can be managed and overcome. The authors also give an overview of the recently published new standard, which is called: OPC unified approach. After the fundamentals are described in this paper, the authors present their experiences with OPC to combine it with methods and procedures to develop a modern maintenance system. It also reports current developments at the department of computer architecture and system Programming at the University of Kassel.

关键词： Industrial research

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Design of a Novel Safe Approach to Monitor Drivers While Operating Their Cars 7

Design of a Novel Safe Approach to Monitor Drivers While Ope...

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7th International Conference on Advances in Biomedical Engineering, ICABME 2023

作者： Elhawawsha, Aseel Zeine, Carla Zeid Daou, Roy Abi Kalinowski, Dominik Khattar, Joseph Telawi, Samer Boercsoek, Josef University of Kassel Department of Computer Architecture and System Programming Kassel Germany Université la Sagesse Saculty of Engineering Mechatronics Eng. Department Beirut Lebanon

ISBN: (纸本)9798350325850

Road accidents have been known to be one of the leading death causes around the world for a long time. Thus, cars and all kinds of road vehicles form a huge source of danger, and they relate to multiple high risks. There are many factors that can contribute to road traffic accidents such as the health condition of the driver if a medical emergency event happened while driving, drowsiness, or mind-wandering. The proposed system can monitor the behavior of the driver while driving as well as his/her health status. Moreover, it analyzes the monitored data, alerts the driver in a timely manner, and assists him/her in adjusting the driving behavior. Different dangerous and risky situations which can be faced during driving can be captured and avoided by using such a system which leads at the end to increase road traffic safety and reduce vehicle collisions. Notifications are developed in cases of drowsiness, loss of focus, or other concerns that may emerge while driving. However, when the driver's ability to operate the vehicle safely is hampered by a health concern, the implemented system is only able at this stage to alarm the driver itself and the surrounding cars as a first level of alarms. © 2023 IEEE.

关键词： Roads and streets

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Smart Medicine Box system 2

Smart Medicine Box System

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2nd IEEE International Multidisciplinary Conference on Engineering Technology, IMCET 2018

作者： Zeidan, Hiba Karam, Khalil Daou, Roy Abi Zeid Hayek, Ali Boercsoek, Josef Biomedical Technologies Department Lebanese German University Faculty of Public Health Jounieh Lebanon Department of Computer Architecture and System Programming Kassel University Kassel Germany

ISBN: (纸本)9781538645000

An advanced medicine box monitoring, analysis and control system is proposed in this paper. The latter design is based on a smart and safe medical box that assists patients in taking their pills treatment on time. Two main functionalities characterize this system: safety which assures the wellbeing of the patient and the good functioning of the system by duplicating the electrical components and the security that helps keeping the medication out of the reach of the children by automatically looking the medical box whenever the patient takes his pills. This system can also be monitored by the patient parents as it will be linked to a phone application. This application will be used to configure the medical box by calculating the weight of each pill, setting the schedule of medical intake, alarming the user of the number of remaining pills, generating alarms whenever the patient does not take the required number of pills or doesn't take them at all, and so on... This system was implemented and tested by more than 50 patients who were taking several medication types (each one of them takes one medication only) and were using different mobile phone. The overall results were very acceptable with a faulty alarm generation below 3%. © 2018 IEEE.

关键词： Pelletizing

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Profile guided optimization for dataflow predication

Profile guided optimization for dataflow predication

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Li, Wang Hong, An Yongqing, Ren Yaobin, Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424426836

Dataflow predication provides a lightweight full support for predicated execution in dataflow-like architectures. One of its major overhead is the large amounts of fanout trees for distributing predicates to all dependant instructions. Conventional optimizations are predicating only the heads or tails of dataflow chains. Predicating tails offers more speculation but leads to resource contentions and power consumption increasing. Predicating heads is power efficient but reduces speculation and instruction level parallelism. This paper introduces a profile guided technique to combine these optimizations. It uses profiling feedback to guide the compiler in deciding to predicate at the head or tail. By predicating tails on hot paths and predicating heads on infrequent paths, this technique can get performance, power and resource efficiency Performance evaluation result shows that profile guided optimization performs better in removing fanout trees. It has 10.6% speedup over always predicating heads and 2.5% speedup over always predicating tails in performance. © 2008 IEEE.

关键词： Forestry

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A Wire delay scalable stream processor architecture

A Wire delay scalable stream processor architecture

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Guang, Xu Hong, An Ming, Cong Fang, Wang Yongqing, Ren Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Science Beijing 100080 China

ISBN: (纸本)9781424426836

Growing on-chip wire delays will cause many future microarchitecture to be distributed. The centralized control and data transmission of the conventional stream processor need to be improved, the hardware resources within a single stream processor become tiles on one or more switched micronetworks. In this paper, we introduce the architecture of the tiled stream processor which aims to adapt to the increasing wire resistance. The tiled stream processor consists of tile arrays, the distributed control and data network which connect tiles. The tile arrays include the five type of reused tiles, the control packet transferred in the control network traverse the tile in a cycle. The architecture of the tiled stream processor supports explicit data management in the hardware way and include two level register hierarchy which are controlled by the software to capture the data locality. The tiled stream processor use the stream programming model which are StreamC/KernelC language, the kernel microcode executed in the tiled arrays are statically scheduled into instruction blocks and execute dynamically in an dataflow order. Finally, we discuss features that affect the kernel performance, with the one cycle routing delay the simulator can achieve an average of 10IPC in eight kernels. © 2008 IEEE.

关键词： computer architecture

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Efficient optimization methodology in early-stage design of mesh-structured on-chip Power/Ground (P/G) networks

Efficient optimization methodology in early-stage design of ...

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Luo, Zu-Ying Department of Electronics Beijing Normal University Beijing 100875 China Key Laboratory of Computer System and Architecture ICT CAS Beijing 100080 China

ISBN: (纸本)1424401615

Due to decreasing supply voltages and increasing power consumption of today's VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during floor-planning stage in the today's physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floor-planning for efficiently minimizing the worst-case IR drop subject to limited routing resource in early-stage P/G network design of high-end chips. In this paper, we present a novel feasible methodology to efficiently optimize the problem of mesh-structured center-bumped P/G grids under given routing resources. In [11], we have proposed the approximate current distribution (ACD) simulation method and the OS_SMACD optimization approach for early-stage single-level P/G meshes]. In this work, a feasible theory is induced to directly compute the optimal solutions OS_DMACD for practical double-mesh P/G grids of high-end chips. Experimental results show that OS_DMACD matches very well with the exact counterparts inefficiently obtained with ICCG, which can leads to significant speedup in the today IR-drop aware floor-planning. © 2006 IEEE.

关键词： VLSI circuits

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Mapping Quantum Circuits to 2-Dimensional Quantum architectures

Mapping Quantum Circuits to 2-Dimensional Quantum Architectu...

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2022 Informatik in den Naturwissenschaften, INFORMATIK 2022 - 2022 computer Science in the Natural Sciences, INFORMATIK 2022

作者： Datta, Kamalika Kole, Abhoy Sengupta, Indranil Drechsler, Rolf Cyber Physical System Bremen Germany JIS University Department of Computer Science and Engineering Kolkata India Indian Institute of Technology Kharagpur Department of Computer Science and Engineering India University of Bremen Group of Computer Architecture Bremen Germany

ISBN: (纸本)9783885797203

We have been witnessing a rapid growth in quantum computing research over the years, with the emergence of demonstrable quantum computers of moderate size. The major issues that are faced to run a quantum algorithm reliably on these systems are: (i) lower qubit coherence period, (ii) noisy primitive gate operations, (iii) limited number of available physical qubits, and (iv) support of restricted set of 2-qubit operations. Overcoming these issues mandates physical resources that exceeds the capabilities of these noisy intermediate scale quantum (NISQ) systems. On the other hand, computation using bare qubits get further disturbed due to the inclusion of additional gates to mitigate the nearest neighbor constraints. In the present work, the 2-dimensional square, heavy-hex and fully hexagonal qubit coupling lattices are considered for mapping quantum circuits. The benefits are assessed in terms of minimal additional gates needed to satisfy the nearest neighbor (NN) constraint and the compilation complexity of mapping circuits on these architectures. From the experiments by mapping benchmark circuits on 16-qubit square and 65-qubit heavy-hex architectures from IBM as well as on a 64-qubit fully hexagonal architecture, it is observed that none of the square or heavy-hex lattice architecture provides uniform compilation advantage compared to the fully hexagonal architecture. It is expected that beyond the NISQ era, strongly connected lattices like hexagonal will become practically feasible. © 2022 Gesellschaft fur Informatik (GI). All rights reserved.

关键词： Qubits

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Parallelizing a machine translation decoder for multicore computer

Parallelizing a machine translation decoder for multicore co...

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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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Effects of varying diagnostic coverage on functional safety

Effects of varying diagnostic coverage on functional safety

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2014 International Symposium on Fundamentals of Electrical Engineering, ISFEE 2014

作者： Üstoʇlu, Ilker Kaymakçi, Özgür T. Börcsök, Josef Department of Control and Automation Engineering Yildiz Technical University Esenler Istanbul34220 Turkey Department of Computer Architecture and System Programming University of Kassel Kassel34121 Germany

ISBN: (纸本)9781479968213

Diagnostics is one of the significant parameters of functional safety which concerns itself with revealing dangerous incidents that might impede the operation of safety systems. Diagnostic coverage factor (DC) is defined as a metric for diagnostics in that DC is one of the most important design parameters to measure the effectiveness of safety protection systems. This study addresses how diagnostics impacts proof test interval (TI) when the system is halted completely;a thorough maintenance and changes in parts are performed. Besides this, the relationship between average probability of failure on demand (PFDavg), DC, TI and mean time to failure (MTTF) are presented for 1oo2 and 1oo2D system architectures. © 2014 IEEE.

关键词： Safety factor

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